Lines Matching +full:hardware +full:- +full:triggered
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
19 triggered or level triggered interrupts and that is fixed in hardware.
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
26 +-------+ | +------+ +-----+ | controller
27 | . . | +-------+
28 +-------+ | . . |----->| IRQ |
29 | INTA |----------->| . . | +-------+
30 +-------+ | . +-----+ |
31 | +------+ | N | |
32 | | irqM | +-----+ |
33 | +------+ |
35 +----------------------+
51 const: ti,sci-intr
53 ti,intr-trigger-type:
58 1 = If intr supports edge triggered interrupts.
59 4 = If intr supports level triggered interrupts.
61 interrupt-controller: true
63 '#interrupt-cells':
68 ti,interrupt-ranges:
69 $ref: /schemas/types.yaml#/definitions/uint32-matrix
75 - description: |
77 - description: |
79 - description: |
83 - compatible
84 - ti,intr-trigger-type
85 - interrupt-controller
86 - '#interrupt-cells'
87 - ti,sci
88 - ti,sci-dev-id
89 - ti,interrupt-ranges
94 - |
95 main_gpio_intr: interrupt-controller0 {
96 compatible = "ti,sci-intr";
97 ti,intr-trigger-type = <1>;
98 interrupt-controller;
99 interrupt-parent = <&gic500>;
100 #interrupt-cells = <1>;
102 ti,sci-dev-id = <131>;
103 ti,interrupt-ranges = <0 360 32>;