Lines Matching +full:single +full:- +full:cell
2 -------------------
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
12 --------------------
13 - compatible: Should be "ti,c64x+core-pic";
14 - #interrupt-cells: <1>
17 ------------------------------
18 Single cell specifying the core interrupt priority level (4-15) where
22 -------
23 core_pic: interrupt-controller@0 {
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 compatible = "ti,c64x+core-pic";
34 combine up to 32 interrupt inputs into a single interrupt output which
44 --------------------
45 - compatible: "ti,c64x+megamod-pic"
46 - interrupt-controller
47 - #interrupt-cells: <1>
48 - reg: base address and size of register area
49 - interrupts: This should have four cells; one for each interrupt combiner.
54 --------------------
55 - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
56 priority interrupts. The first cell corresponds to
57 core priority 4 and the last cell corresponds to
58 core priority 15. The value of each cell is the
60 the core interrupt corresponding to the cell
61 position. Allowed values are 4 - 127. Mapping for
62 interrupts 0 - 3 (combined interrupt sources) are
66 ------------------------------
67 Single cell specifying the megamodule interrupt source (4-127). Note that
68 interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
73 --------
74 megamod_pic: interrupt-controller@1800000 {
75 compatible = "ti,c64x+megamod-pic";
76 interrupt-controller;
77 #interrupt-cells = <1>;
79 interrupt-parent = <&core_pic>;
84 combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
88 megamod_pic: interrupt-controller@1800000 {
89 compatible = "ti,c64x+megamod-pic";
90 interrupt-controller;
91 #interrupt-cells = <1>;
93 interrupt-parent = <&core_pic>;
95 ti,c64x+megamod-pic-mux = < 0 0 0 0