Lines Matching full:gic
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
13 ARM SMP cores are often associated with a GIC, providing per processor
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
34 - arm,eb11mp-gic
35 - arm,gic-400
37 - arm,tc11mp-gic
43 - const: arm,gic-400
45 - arm,cortex-a15-gic
46 - arm,cortex-a7-gic
49 - const: arm,arm1176jzf-devchip-gic
50 - const: arm,arm11mp-gic
53 - const: brcm,brahma-b15-gic
54 - const: arm,cortex-a15-gic
80 the 8 possible cpus attached to the GIC. A bit set to '1' indicated
89 Specifies base physical address(s) and size of the GIC registers. The
90 first region is the GIC distributor register base and size. The 2nd region
91 is the GIC cpu interface register base and size.
95 registers. The first additional region is the GIC virtual interface
96 control register base and size. The 2nd additional region is the GIC
105 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
111 regions, used when the GIC doesn't have banked registers. The offset
120 description: List of names for the GIC clock input(s). Valid clock names
121 depend on the GIC variant.
123 - const: ic_clk # for "arm,arm11mp-gic"
124 - const: PERIPHCLKEN # for "arm,cortex-a15-gic"
125 - items: # for "arm,cortex-a9-gic"
128 - const: clk # for "arm,gic-400" and "nvidia,tegra210"
147 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
152 const: arm,gic-v2m-frame
185 compatible = "arm,cortex-a9-gic";
196 compatible = "arm,cortex-a15-gic";
209 compatible = "arm,gic-400";
222 compatible = "arm,gic-v2m-frame";
230 compatible = "arm,gic-v2m-frame";