Lines Matching +full:0 +full:x2c080000
33 enum: [ 0, 1, 2 ]
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extented SPI interrupts are in the range [0-1023].
53 Extended PPI interrupts are in the range [0-127].
56 bits[3:0] trigger type and level flags.
68 of 0 if present.
95 multipleOf: 0x10000
96 exclusiveMinimum: 0
136 "^interrupt-partition-[0-9]+$":
159 "^interrupt-controller@[0-9a-f]+$": false
161 "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
211 reg = <0x2f000000 0x10000>, // GICD
212 <0x2f100000 0x200000>, // GICR
213 <0x2c000000 0x2000>, // GICC
214 <0x2c010000 0x2000>, // GICH
215 <0x2c020000 0x2000>; // GICV
225 reg = <0x2c200000 0x20000>;
236 redistributor-stride = <0x0 0x40000>; // 256kB stride
238 reg = <0x2c010000 0x10000>, // GICD
239 <0x2d000000 0x800000>, // GICR 1: CPUs 0-31
240 <0x2e000000 0x800000>, // GICR 2: CPUs 32-63
241 <0x2c040000 0x2000>, // GICC
242 <0x2c060000 0x2000>, // GICH
243 <0x2c080000 0x2000>; // GICV
250 reg = <0x2c200000 0x20000>;
257 reg = <0x2c400000 0x20000>;
261 part0: interrupt-partition-0 {
272 device@0 {
273 reg = <0 4>;