Lines Matching +full:opp +full:- +full:133 +full:m
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Leonard Crestez <leonard.crestez@nxp.com>
18 for normal (non-secure) world.
20 The buses are based on externally licensed IPs such as ARM NIC-301 and
27 - items:
28 - enum:
29 - fsl,imx8mn-nic
30 - fsl,imx8mm-nic
31 - fsl,imx8mq-nic
32 - const: fsl,imx8m-nic
33 - items:
34 - enum:
35 - fsl,imx8mn-noc
36 - fsl,imx8mm-noc
37 - fsl,imx8mq-noc
38 - const: fsl,imx8m-noc
39 - const: fsl,imx8m-nic
47 operating-points-v2: true
48 opp-table: true
55 '#interconnect-cells':
62 - compatible
63 - clocks
68 - |
69 #include <dt-bindings/clock/imx8mm-clock.h>
70 #include <dt-bindings/interconnect/imx8mm.h>
71 #include <dt-bindings/interrupt-controller/arm-gic.h>
74 compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc";
77 #interconnect-cells = <1>;
80 operating-points-v2 = <&noc_opp_table>;
81 noc_opp_table: opp-table {
82 compatible = "operating-points-v2";
84 opp-133M {
85 opp-hz = /bits/ 64 <133333333>;
87 opp-800M {
88 opp-hz = /bits/ 64 <800000000>;
93 ddrc: memory-controller@3d400000 {
94 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
96 clock-names = "core", "pll", "alt", "apb";