Lines Matching +full:min +full:- +full:sample +full:- +full:time
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 STM32 ADC is a successive approximation analog-to-digital converter.
13 stored in a left-aligned or right-aligned 32-bit data register.
17 voltage goes beyond the user-defined, higher or lower thresholds.
22 - Fabrice Gasnier <fabrice.gasnier@st.com>
27 - st,stm32f4-adc-core
28 - st,stm32h7-adc-core
29 - st,stm32mp1-adc-core
37 - stm32f4 and stm32h7 share a common ADC interrupt line.
38 - stm32mp1 has two separate interrupt lines, one for each ADC within
46 - "adc" clock: for the analog circuitry, common to all ADCs.
49 - "bus" clock: for registers access, common to all ADCs.
53 clock-names: true
55 st,max-clk-rate-hz:
59 vdda-supply:
62 vref-supply:
65 booster-supply:
70 vdd-supply:
79 $ref: "/schemas/types.yaml#/definitions/phandle-array"
81 interrupt-controller: true
83 '#interrupt-cells':
86 '#address-cells':
89 '#size-cells':
93 - if:
97 const: st,stm32f4-adc-core
104 clock-names:
109 - description: interrupt line common for all ADCs
111 st,max-clk-rate-hz:
116 booster-supply: false
118 vdd-supply: false
122 - if:
126 const: st,stm32h7-adc-core
134 clock-names:
136 - const: bus
137 - const: adc
143 - description: interrupt line common for all ADCs
145 st,max-clk-rate-hz:
150 vdd-supply: false
154 - if:
158 const: st,stm32mp1-adc-core
166 clock-names:
168 - const: bus
169 - const: adc
175 - description: interrupt line for ADC1
176 - description: interrupt line for ADC2
178 st,max-clk-rate-hz:
186 - compatible
187 - reg
188 - interrupts
189 - clocks
190 - clock-names
191 - vdda-supply
192 - vref-supply
193 - interrupt-controller
194 - '#interrupt-cells'
195 - '#address-cells'
196 - '#size-cells'
199 "^adc@[0-9]+$":
208 - st,stm32f4-adc
209 - st,stm32h7-adc
210 - st,stm32mp1-adc
215 - 0x0: ADC1
216 - 0x100: ADC2
217 - 0x200: ADC3 (stm32f4 only)
220 '#io-channel-cells':
226 - 0 for adc@0
227 - 1 for adc@100
228 - 2 for adc@200 (stm32f4 only)
241 dma-names:
244 assigned-resolution-bits:
247 - can be 6, 8, 10 or 12 on stm32f4
248 - can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
251 st,adc-channels:
253 List of single-ended channels muxed for this ADC. It can have up to:
254 - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
255 - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
257 $ref: /schemas/types.yaml#/definitions/uint32-array
259 st,adc-diff-channels:
262 be configured as differential instead of single-ended on stm32h7 and
266 Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
268 used as single-ended and some other ones as differential (mixed). But
269 channels can't be configured both as single-ended and differential.
270 $ref: /schemas/types.yaml#/definitions/uint32-matrix
273 - description: |
277 - description: |
282 st,min-sample-time-nsecs:
284 Minimum sampling time in nanoseconds. Depending on hardware (board)
286 sampling time may be recommended. This can be either one value or an
287 array that matches "st,adc-channels" and/or "st,adc-diff-channels"
288 list, to set sample time resp. for all channels, or independently for
290 $ref: /schemas/types.yaml#/definitions/uint32-array
293 - if:
297 const: st,stm32f4-adc
303 - 0x0
304 - 0x100
305 - 0x200
311 assigned-resolution-bits:
315 st,adc-channels:
322 st,adc-diff-channels: false
324 st,min-sample-time-nsecs:
331 - clocks
333 - if:
338 - st,stm32h7-adc
339 - st,stm32mp1-adc
345 - 0x0
346 - 0x100
352 assigned-resolution-bits:
356 st,adc-channels:
363 st,min-sample-time-nsecs:
372 - required:
373 - st,adc-channels
374 - required:
375 - st,adc-diff-channels
378 - compatible
379 - reg
380 - interrupts
381 - '#io-channel-cells'
384 - |
385 // Example 1: with stm32f429, ADC1, single-ended channel 8
387 compatible = "st,stm32f4-adc-core";
391 clock-names = "adc";
392 st,max-clk-rate-hz = <36000000>;
393 vdda-supply = <&vdda>;
394 vref-supply = <&vref>;
395 interrupt-controller;
396 #interrupt-cells = <1>;
397 #address-cells = <1>;
398 #size-cells = <0>;
400 compatible = "st,stm32f4-adc";
401 #io-channel-cells = <1>;
404 interrupt-parent = <&adc123>;
406 st,adc-channels = <8>;
408 dma-names = "rx";
409 assigned-resolution-bits = <8>;
415 - |
417 // - channels 0 & 1 as single-ended
418 // - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
419 #include <dt-bindings/interrupt-controller/arm-gic.h>
420 #include <dt-bindings/clock/stm32mp1-clks.h>
422 compatible = "st,stm32mp1-adc-core";
427 clock-names = "bus", "adc";
428 booster-supply = <&booster>;
429 vdd-supply = <&vdd>;
430 vdda-supply = <&vdda>;
431 vref-supply = <&vref>;
433 interrupt-controller;
434 #interrupt-cells = <1>;
435 #address-cells = <1>;
436 #size-cells = <0>;
438 compatible = "st,stm32mp1-adc";
439 #io-channel-cells = <1>;
441 interrupt-parent = <&adc12>;
443 st,adc-channels = <0 1>;
444 st,adc-diff-channels = <2 6>, <3 7>;
445 st,min-sample-time-nsecs = <5000>;
447 dma-names = "rx";