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4 controller. This binding document applies to both controllers. The register
5 layouts for the controllers share many similarities, but also some significant
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
14 a) Security registers, which allow configuration of allowed access to the GPIO
19 Access to this set of registers is not necessary in all circumstances. Code
20 that wishes to configure access to the GPIO registers needs access to these
21 registers to do so. Code which simply wishes to read or write GPIO data does not
22 need access to these registers.
27 documentation for rationale. Any particular GPIO client is expected to access
28 just one of these physical aliases.
31 implemented by the SoC. Each GPIO is assigned to a port, and a port may control
32 a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
38 are grouped and laid out according to the port they affect.
40 The mapping from port name to the GPIO controller that implements that port, and
41 the mapping from port name to register offset within a controller, are both
42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
43 describes the port-level mapping. In that file, the naming convention for ports
45 sorted within a particular controller. Drivers need to map between the DT GPIO
51 of the number of ports it implements. Note that the HW documentation refers to
52 both the overall controller HW module and the sets-of-ports as "controllers".
55 of ports. Each GPIO may be configured to feed into a specific one of the
56 interrupt signals generated by a set-of-ports. The intent is for each generated
57 signal to be routed to a different CPU, thus allowing different CPUs to each
59 per-port-set signals is reported via a separate register. Thus, a driver needs
60 to know which status register to observe. This binding currently defines no
62 GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
63 define a property to configure this.
66 - compatible
68 One of:
69 - "nvidia,tegra186-gpio".
70 - "nvidia,tegra186-gpio-aon".
71 - "nvidia,tegra194-gpio".
72 - "nvidia,tegra194-gpio-aon".
73 - reg-names
77 - "gpio": Mandatory. GPIO control registers. This may cover either:
82 - "security": Optional. Security configuration registers.
84 using this reg-names property to do so.
85 - reg
87 Must contain one entry per entry in the reg-names property, in a matching
89 - interrupts
91 The interrupt outputs from the HW block, one per set of ports, in the
94 - "nvidia,tegra186-gpio": 6 entries.
95 - "nvidia,tegra186-gpio-aon": 1 entry.
96 - "nvidia,tegra194-gpio": 6 entries.
97 - "nvidia,tegra194-gpio-aon": 1 entry.
98 - gpio-controller
101 - #gpio-cells
102 Single-cell integer.
104 Indicates how many cells are used in a consumer's GPIO specifier.
106 - The first cell is the pin number.
107 See <dt-bindings/gpio/tegra186-gpio.h>.
108 - The second cell contains flags:
109 - Bit 0 specifies polarity
110 - 0: Active-high (normal).
111 - 1: Active-low (inverted).
112 - interrupt-controller
115 - #interrupt-cells
116 Single-cell integer.
118 Indicates how many cells are used in a consumer's interrupt specifier.
120 - The first cell is the GPIO number.
121 See <dt-bindings/gpio/tegra186-gpio.h>.
122 - The second cell is contains flags:
123 - Bits [3:0] indicate trigger type and level:
124 - 1: Low-to-high edge triggered.
125 - 2: High-to-low edge triggered.
126 - 4: Active high level-sensitive.
127 - 8: Active low level-sensitive.
132 #include <dt-bindings/interrupt-controller/irq.h>
135 compatible = "nvidia,tegra186-gpio";
136 reg-names = "security", "gpio";
147 gpio-controller;
148 #gpio-cells = <2>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
154 compatible = "nvidia,tegra186-gpio-aon";
155 reg-names = "security", "gpio";
161 gpio-controller;
162 #gpio-cells = <2>;
163 interrupt-controller;
164 #interrupt-cells = <2>;