Lines Matching +full:gpio +full:- +full:reserved +full:- +full:ranges
1 Specifying GPIO information for devices
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
23 The following example could be used to describe GPIO pins used as device enable
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
37 In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is
38 a local offset to the GPIO line and the second cell represent consumer flags,
44 recommended to use the two-cell approach.
48 include/dt-bindings/gpio/gpio.h whenever possible:
53 enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>;
56 GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes
57 GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
61 - Bit 0: 0 means active high, 1 means active low
62 - Bit 1: 0 mean push-pull wiring, see:
63 https://en.wikipedia.org/wiki/Push-pull_output
64 1 means single-ended wiring, see:
65 https://en.wikipedia.org/wiki/Single-ended_triode
66 - Bit 2: 0 means open-source, 1 means open drain, see:
68 - Bit 3: 0 means the output should be maintained during sleep/low-power mode
69 1 means the output state can be lost during sleep/low-power mode
70 - Bit 4: 0 means no pull-up resistor should be enabled
71 1 means a pull-up resistor should be enabled
73 control for pull-up configuration. If the hardware has more
74 elaborate pull-up configuration, it should be represented
76 - Bit 5: 0 means no pull-down resistor should be enabled
77 1 means a pull-down resistor should be enabled
79 control for pull-down configuration. If the hardware has more
80 elaborate pull-down configuration, it should be represented
83 1.1) GPIO specifier best practices
84 ----------------------------------
86 A gpio-specifier should contain a flag indicating the GPIO polarity; active-
87 high or active-low. If it does, the following best practices should be
90 The gpio-specifier's polarity flag should represent the physical level at the
91 GPIO controller that achieves (or represents, for inputs) a logically asserted
94 the GPIO controller and the device, then the gpio-specifier will represent the
106 a1) (Preferred) Dictated by a binding-specific DT property.
112 In particular, the polarity cannot be derived from the gpio-specifier, since
114 concepts of configurable signal polarity in the device, and possible board-
120 in the binding. The gpio-specifier should represent the polarity of the signal
121 (at the GPIO controller) assuming that the device is configured for this
124 responsible for correctly interpreting (inverting) the GPIO signal at the GPIO
127 2) gpio-controller nodes
128 ------------------------
130 Every GPIO controller node must contain both an empty "gpio-controller"
131 property, and a #gpio-cells integer property, which indicates the number of
132 cells in a gpio-specifier.
134 Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an
137 exposed in the device tree as an individual gpio-controller node, reflecting
141 Optionally, a GPIO controller may have a "ngpios" property. This property
142 indicates the number of in-use slots of available slots for GPIOs. The
150 If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an
152 the gpio-reserved-ranges binding. This property indicates the start and size
155 Optionally, a GPIO controller may have a "gpio-line-names" property. This is
156 an array of strings defining the names of the GPIO lines going out of the
157 GPIO controller. This name should be the most meaningful producer name
161 helpful. For example "MMC-CD", "Red LED Vdd" and "ethernet reset" are
163 is not a good name to give to a GPIO line. Placeholders are discouraged:
164 rather use the "" (blank string) if the use of the GPIO line is undefined
172 gpio-controller@00000000 {
175 gpio-controller;
176 #gpio-cells = <2>;
178 gpio-reserved-ranges = <0 4>, <12 2>;
179 gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R",
185 The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism
186 providing automatic GPIO request and configuration as part of the
187 gpio-controller's driver probe function.
189 Each GPIO hog definition is represented as a child node of the GPIO controller.
191 - gpio-hog: A property specifying that this child node represents a GPIO hog.
192 - gpios: Store the GPIO information (id, flags, ...) for each GPIO to
194 specified in its parent node (GPIO controller node).
199 - input: A property specifying to set the GPIO direction as input.
200 - output-low A property specifying to set the GPIO direction as output with
202 - output-high A property specifying to set the GPIO direction as output with
206 - line-name: The GPIO label name. If not present the node name is used.
208 Example of two SOC GPIO banks defined as gpio-controller nodes:
210 qe_pio_a: gpio-controller@1400 {
211 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank";
213 gpio-controller;
214 #gpio-cells = <2>;
217 gpio-hog;
219 output-low;
220 line-name = "foo-bar-gpio";
224 qe_pio_e: gpio-controller@1460 {
225 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
227 gpio-controller;
228 #gpio-cells = <2>;
231 2.1) gpio- and pin-controller interaction
232 -----------------------------------------
234 Some or all of the GPIOs provided by a GPIO controller may be routed to pins
236 GPIO and other functions. It is a fairly common practice among silicon
239 2.2) Ordinary (numerical) GPIO ranges
240 -------------------------------------
243 controllers. The gpio-ranges property described below represents this with
244 a discrete set of ranges mapping pins from the pin controller local number space
245 to pins in the GPIO controller local number space.
247 The format is: <[pin controller phandle], [GPIO controller offset],
250 The GPIO controller offset pertains to the GPIO controller node containing the
254 described in pinctrl/pinctrl-bindings.txt.
257 ranges with just one pin-to-GPIO line mapping if the ranges are concocted, but
258 in practice these ranges are often lumped in discrete sets.
262 gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>;
265 - pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9 and
266 - pins 50..69 on pin controller "bar" is mapped to GPIO line 10..29
271 qe_pio_e: gpio-controller@1460 {
272 #gpio-cells = <2>;
273 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
275 gpio-controller;
276 gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
279 Here, a single GPIO controller has GPIOs 0..9 routed to pin controller
284 2.3) GPIO ranges from named pin groups
285 --------------------------------------
287 It is also possible to use pin groups for gpio ranges when pin groups are the
290 Both both <pinctrl-base> and <count> must set to 0 when using named pin groups
293 The property gpio-ranges-group-names must contain exactly one string for each
296 Elements of gpio-ranges-group-names must contain the name of a pin group
297 defined in the respective pin controller. The number of pins/GPIO lines in the
302 numerical pin range in gpio-ranges-group-names must be empty.
306 gpio_pio_i: gpio-controller@14b0 {
307 #gpio-cells = <2>;
308 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
310 gpio-controller;
311 gpio-ranges = <&pinctrl1 0 20 10>,
315 gpio-ranges-group-names = "",
321 Here, three GPIO ranges are defined referring to two pin controllers.
323 pinctrl1 GPIO ranges are defined using pin numbers whereas the GPIO ranges
327 were referenced by any gpio-ranges property to contain a property named
328 #gpio-range-cells with value <3>. This requirement is now deprecated.