Lines Matching +full:multi +full:- +full:channel
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: "dma-controller.yaml#"
18 const: snps,dma-spear1340
20 "#dma-cells":
26 for transfers on dynamically allocated channel. Fourth cell is the
27 peripheral master identifier for transfers on an allocated channel. Fifth
40 clock-names:
44 dma-channels:
47 not specified the driver will try to auto-detect this and
52 dma-requests:
56 dma-masters:
60 not specified the driver will try to auto-detect this and
69 (first free allocated), while one - descending (last free allocated).
77 so the very first channel has the highest priority. While 1 means
78 descending priority (the last channel has the highest priority).
87 data-width:
88 $ref: /schemas/types.yaml#/definitions/uint32-array
96 $ref: /schemas/types.yaml#/definitions/uint32-array
100 deprecated. It' usage is discouraged in favor of data-width one. Moreover
101 the property incorrectly permits to define data-bus width of 8 and 16
102 bits, which is impossible in accordance with DW DMAC IP-core data book.
107 - 0 # 8 bits
108 - 1 # 16 bits
109 - 2 # 32 bits
110 - 3 # 64 bits
111 - 4 # 128 bits
112 - 5 # 256 bits
115 multi-block:
116 $ref: /schemas/types.yaml#/definitions/uint32-array
118 LLP-based multi-block transfer supported by hardware per
119 each DMA channel.
126 snps,max-burst-len:
127 $ref: /schemas/types.yaml#/definitions/uint32-array
130 This property defines the upper limit of the run-time burst setting
132 will be from 1 to max-burst-len words. It's an array property with one
133 cell per channel in the units determined by the value set in the
141 snps,dma-protection-control:
144 Bits one-to-one passed to the AHB HPROT[3:1] bus. Each bit setting
145 indicates the following features: bit 0 - privileged mode,
146 bit 1 - DMA is bufferable, bit 2 - DMA is cacheable.
154 - compatible
155 - "#dma-cells"
156 - reg
157 - interrupts
160 - |
161 dma-controller@fc000000 {
162 compatible = "snps,dma-spear1340";
164 interrupt-parent = <&vic1>;
167 dma-channels = <8>;
168 dma-requests = <16>;
169 dma-masters = <4>;
170 #dma-cells = <3>;
175 data-width = <8 8>;
176 multi-block = <0 0 0 0 0 0 0 0>;
177 snps,max-burst-len = <16 16 4 4 4 4 4 4>;