Lines Matching full:sdma
1 * Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
5 "fsl,imx25-sdma"
6 "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
7 "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
8 "fsl,imx51-sdma"
9 "fsl,imx53-sdma"
10 "fsl,imx6q-sdma"
11 "fsl,imx7d-sdma"
12 "fsl,imx8mq-sdma"
13 "fsl,imx8mm-sdma"
14 "fsl,imx8mn-sdma"
15 "fsl,imx8mp-sdma"
19 - reg : Should contain SDMA registers location and length
20 - interrupts : Should contain SDMA interrupt
24 - fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
69 - fsl,sdma-event-remap : Register bits of sdma event remap, the format is
77 sdma@83fb0000 {
78 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
82 fsl,sdma-ram-script-name = "sdma-imx51.bin";
85 DMA clients connected to the i.MX SDMA controller must use the format
95 dmas = <&sdma 24 1 0>,
96 <&sdma 25 1 0>;
101 Using the fsl,sdma-event-remap property:
103 If we want to use SDMA on the SAI1 port on a MX6SX:
105 &sdma {
107 /* SDMA events remap for SAI1_RX and SAI1_TX */
108 fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
111 The fsl,sdma-event-remap property in this case has two values:
113 SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX.
116 SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX.