Lines Matching +full:designware +full:- +full:i2c

4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
9 following device-specific properties.
14 - compatible: should be one of the following:
15 		"rockchip,rk3228-dw-hdmi"
16 		"rockchip,rk3288-dw-hdmi"
17 		"rockchip,rk3328-dw-hdmi"
18 		"rockchip,rk3399-dw-hdmi"
19 - reg: See dw_hdmi.txt.
20 - reg-io-width: See dw_hdmi.txt. Shall be 4.
21 - interrupts: HDMI interrupt number
22 - clocks: See dw_hdmi.txt.
23 - clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
24 - ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
27 - rockchip,grf: Shall reference the GRF to mux vopl/vopb.
31 - ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master
32   or the functionally-reduced I2C master contained in the DWC HDMI. When
33   connected to a system I2C master this property contains a phandle to that
34   I2C master controller.
35 - clock-names: See dw_hdmi.txt. The "cec" clock is optional.
36 - clock-names: May contain "cec" as defined in dw_hdmi.txt.
37 - clock-names: May contain "grf", power for grf io.
38 - clock-names: May contain "vpll", external clock for some hdmi phy.
39 - phys: from general PHY binding: the phandle for the PHY device.
40 - phy-names: Should be "hdmi" if phys references an external phy.
43 - If you have both a "unwedge" and "default" pinctrl entry, dw_hdmi
45   i2c timeout.  It's intended that this unwedge pinctrl entry will
52 	compatible = "rockchip,rk3288-dw-hdmi";
54 	reg-io-width = <4>;
55 	ddc-i2c-bus = <&i2c5>;
59 	clock-names = "iahb", "isfr";
62 			#address-cells = <1>;
63 			#size-cells = <0>;
66 				remote-endpoint = <&vopb_out_hdmi>;
70 				remote-endpoint = <&vopl_out_hdmi>;