Lines Matching +full:adreno +full:- +full:gmu
1 # SPDX-License-Identifier: GPL-2.0-only
2 # Copyright 2019-2020, The Linux Foundation, All Rights Reserved
4 ---
6 $id: "http://devicetree.org/schemas/display/msm/gmu.yaml#"
7 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
9 title: Devicetree bindings for the GMU attached to certain Adreno GPUs
12 - Rob Clark <robdclark@gmail.com>
15 These bindings describe the Graphics Management Unit (GMU) that is attached
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
23 - enum:
24 - qcom,adreno-gmu-630.2
25 - const: qcom,adreno-gmu
29 - description: Core GMU registers
30 - description: GMU PDC registers
31 - description: GMU PDC sequence registers
33 reg-names:
35 - const: gmu
36 - const: gmu_pdc
37 - const: gmu_pdc_seq
41 - description: GMU clock
42 - description: GPU CX clock
43 - description: GPU AXI clock
44 - description: GPU MEMNOC clock
46 clock-names:
48 - const: gmu
49 - const: cxo
50 - const: axi
51 - const: memnoc
55 - description: GMU HFI interrupt
56 - description: GMU interrupt
59 interrupt-names:
61 - const: hfi
62 - const: gmu
64 power-domains:
66 - description: CX power domain
67 - description: GX power domain
69 power-domain-names:
71 - const: cx
72 - const: gx
77 operating-points-v2: true
80 - compatible
81 - reg
82 - reg-names
83 - clocks
84 - clock-names
85 - interrupts
86 - interrupt-names
87 - power-domains
88 - power-domain-names
89 - iommus
90 - operating-points-v2
95 - |
96 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
97 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
98 #include <dt-bindings/interrupt-controller/irq.h>
99 #include <dt-bindings/interrupt-controller/arm-gic.h>
101 gmu: gmu@506a000 {
102 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
107 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
113 clock-names = "gmu", "cxo", "axi", "memnoc";
117 interrupt-names = "hfi", "gmu";
119 power-domains = <&gpucc GPU_CX_GDSC>,
121 power-domain-names = "cx", "gx";
124 operating-points-v2 = <&gmu_opp_table>;