Lines Matching +full:display +full:- +full:subsystem
1 Mediatek display subsystem
4 The Mediatek display subsystem consists of various DISP function blocks in the
17 A display stream starts at a source function block that reads pixel data from
18 memory and ends with a sink function block that drives pixels on a display
24 For a description of the display interface sink function blocks, see
25 Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
26 Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt.
29 - compatible: "mediatek,<chip>-disp-<function>", one of
30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33 "mediatek,<chip>-disp-wdma" - write DMA
34 "mediatek,<chip>-disp-ccorr" - color correction
35 "mediatek,<chip>-disp-color" - color processor
36 "mediatek,<chip>-disp-dither" - dither
37 "mediatek,<chip>-disp-aal" - adaptive ambient light controller
38 "mediatek,<chip>-disp-gamma" - gamma correction
39 "mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
40 "mediatek,<chip>-disp-split" - split stream to two encoders
41 "mediatek,<chip>-disp-ufoe" - data compression engine
42 "mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
43 "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
44 "mediatek,<chip>-disp-mutex" - display mutex
45 "mediatek,<chip>-disp-od" - overdrive
47 - reg: Physical base address and length of the function block register space
48 - interrupts: The interrupt signal from the function block (required, except for
50 - clocks: device clocks
51 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
58 - compatible: Should be one of
59 "mediatek,<chip>-disp-ovl"
60 "mediatek,<chip>-disp-rdma"
61 "mediatek,<chip>-disp-wdma"
63 - larb: Should contain a phandle pointing to the local arbiter device as defined
64 in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
65 - iommus: Should point to the respective IOMMU block with master port as
71 mmsys: clock-controller@14000000 {
72 compatible = "mediatek,mt8173-mmsys", "syscon";
74 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
75 #clock-cells = <1>;
79 compatible = "mediatek,mt8173-disp-ovl";
82 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
89 compatible = "mediatek,mt8173-disp-ovl";
92 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
99 compatible = "mediatek,mt8173-disp-rdma";
102 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
109 compatible = "mediatek,mt8173-disp-rdma";
112 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
119 compatible = "mediatek,mt8173-disp-rdma";
122 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
129 compatible = "mediatek,mt8173-disp-wdma";
132 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
139 compatible = "mediatek,mt8173-disp-wdma";
142 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
149 compatible = "mediatek,mt8173-disp-color";
152 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
157 compatible = "mediatek,mt8173-disp-color";
160 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
165 compatible = "mediatek,mt8173-disp-aal";
168 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
173 compatible = "mediatek,mt8173-disp-gamma";
176 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
181 compatible = "mediatek,mt8173-disp-ufoe";
184 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
197 compatible = "mediatek,mt8173-disp-mutex";
200 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
205 compatible = "mediatek,mt8173-disp-od";
207 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;