Lines Matching full:description

13 description:
27       - description: DCSS base address and size, up to IRQ steer start
28       - description: DCSS BLKCTL base address and size
32       - description: Context loader completion and error interrupt
33       - description: DTG interrupt used to signal context loader trigger time
34       - description: DTG interrupt for Vblank
44       - description: Display APB clock for all peripheral PIO access interfaces
45       - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL
46       - description: RTRAM clock
47       - description: Pixel clock, can be driven either by HDMI phy clock or MIPI
48       - description: DTRC clock, needed by video decompressor
60       - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_AXI_ROOT
61       - description: Phandle and clock specifier of IMX8MQ_CLK_DISP_RTRM
62       - description: Phandle and clock specifier of either IMX8MQ_VIDEO2_PLL1_REF_SEL or
67       - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
68       - description: Phandle and clock specifier of IMX8MQ_SYS1_PLL_800M
69       - description: Phandle and clock specifier of IMX8MQ_CLK_27M
73       - description: Must be 800 MHz
74       - description: Must be 400 MHz
78     description: