Lines Matching full:side
75 the ODT on the DRAM side and controller side are
79 the DRAM side driver strength in ohms. Default
83 the DRAM side ODT strength in ohms. Default value
87 the phy side CA line (incluing command line,
92 the PHY side DQ line (including DQS/DQ/DM line)
96 the PHY side ODT strength. Default value is
102 the ODT on the DRAM side and controller side are
106 the DRAM side driver strength in ohms. Default
110 the DRAM side ODT strength in ohms. Default value
114 the PHY side CA line (including command line,
119 the PHY side DQ line (including DQS/DQ/DM line)
124 the phy side odt strength, default value is
130 ddr3_odt_dis_freq, the ODT on the DRAM side and
131 controller side are both disabled.
134 the DRAM side driver strength in ohms. Default
138 the DRAM side ODT on DQS/DQ line strength in ohms.
142 the DRAM side ODT on CA line strength in ohms.
146 the PHY side CA line (including command address
151 the PHY side clock line and CS line driver
155 the PHY side DQ line (including DQS/DQ/DM line)
159 the PHY side ODT strength. Default value is