Lines Matching +full:opp +full:- +full:400000000
4 and sub-blocks in SoC. Most Exynos SoCs share the common architecture
9 is able to measure the current load of sub-blocks.
11 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
13 power line. The power line might be shared among one more sub-blocks.
14 So, we can divide into two type of device as the role of each sub-block.
16 - parent bus device
17 - passive bus device
26 VDD_xxx |--- A block (parent)
27 |--- B block (passive)
28 |--- C block (passive)
31 SoC has different sub-blocks. Therefore, such difference should be specified
36 - compatible: Should be "samsung,exynos-bus".
37 - clock-names : the name of clock used by the bus, "bus".
38 - clocks : phandles for clock specified in "clock-names" property.
39 - operating-points-v2: the OPP table including frequency/voltage information
43 - vdd-supply: the regulator to provide the buses with the voltage.
44 - devfreq-events: the devfreq-event device to monitor the current utilization
48 - devfreq: the parent bus device.
51 - exynos,saturation-ratio: the percentage value which is used to calibrate
54 Detailed correlation between sub-blocks and power line according to Exynos SoC:
55 - In case of Exynos3250, there are two power line as following:
56 VDD_MIF |--- DMC
58 VDD_INT |--- LEFTBUS (parent device)
59 |--- PERIL
60 |--- MFC
61 |--- G3D
62 |--- RIGHTBUS
63 |--- PERIR
64 |--- FSYS
65 |--- LCD0
66 |--- PERIR
67 |--- ISP
68 |--- CAM
70 - In case of Exynos4210, there is one power line as following:
71 VDD_INT |--- DMC (parent device)
72 |--- LEFTBUS
73 |--- PERIL
74 |--- MFC(L)
75 |--- G3D
76 |--- TV
77 |--- LCD0
78 |--- RIGHTBUS
79 |--- PERIR
80 |--- MFC(R)
81 |--- CAM
82 |--- FSYS
83 |--- GPS
84 |--- LCD0
85 |--- LCD1
87 - In case of Exynos4x12, there are two power line as following:
88 VDD_MIF |--- DMC
90 VDD_INT |--- LEFTBUS (parent device)
91 |--- PERIL
92 |--- MFC(L)
93 |--- G3D
94 |--- TV
95 |--- IMAGE
96 |--- RIGHTBUS
97 |--- PERIR
98 |--- MFC(R)
99 |--- CAM
100 |--- FSYS
101 |--- GPS
102 |--- LCD0
103 |--- ISP
105 - In case of Exynos5422, there are two power line as following:
106 VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
107 |--- DREX 1
109 VDD_INT |--- NoC_Core (parent device)
110 |--- G2D
111 |--- G3D
112 |--- DISP1
113 |--- NoC_WCORE
114 |--- GSCL
115 |--- MSCL
116 |--- ISP
117 |--- MFC
118 |--- GEN
119 |--- PERIS
120 |--- PERIC
121 |--- FSYS
122 |--- FSYS2
124 - In case of Exynos5433, there is VDD_INT power line as following:
125 VDD_INT |--- G2D (parent device)
126 |--- MSCL
127 |--- GSCL
128 |--- JPEG
129 |--- MFC
130 |--- HEVC
131 |--- BUS0
132 |--- BUS1
133 |--- BUS2
134 |--- PERIS (Fixed clock rate)
135 |--- PERIC (Fixed clock rate)
136 |--- FSYS (Fixed clock rate)
143 - MIF (Memory Interface) block
144 : VDD_MIF |--- DMC (Dynamic Memory Controller)
146 - INT (Internal) block
147 : VDD_INT |--- LEFTBUS (parent device)
148 |--- PERIL
149 |--- MFC
150 |--- G3D
151 |--- RIGHTBUS
152 |--- FSYS
153 |--- LCD0
154 |--- PERIR
155 |--- ISP
156 |--- CAM
158 - MIF bus's frequency/voltage table
159 -----------------------
161 -----------------------
167 -----------------------
169 - INT bus's frequency/voltage table
170 ----------------------------------------------------------
175 ----------------------------------------------------------
177 ----------------------------------------------------------
179 ----------------------------------------------------------
185 ----------------------------------------------------------
192 compatible = "samsung,exynos-bus";
194 clock-names = "bus";
195 operating-points-v2 = <&bus_dmc_opp_table>;
200 compatible = "operating-points-v2";
201 opp-shared;
203 opp-50000000 {
204 opp-hz = /bits/ 64 <50000000>;
205 opp-microvolt = <800000>;
207 opp-100000000 {
208 opp-hz = /bits/ 64 <100000000>;
209 opp-microvolt = <800000>;
211 opp-134000000 {
212 opp-hz = /bits/ 64 <134000000>;
213 opp-microvolt = <800000>;
215 opp-200000000 {
216 opp-hz = /bits/ 64 <200000000>;
217 opp-microvolt = <825000>;
219 opp-400000000 {
220 opp-hz = /bits/ 64 <400000000>;
221 opp-microvolt = <875000>;
226 compatible = "samsung,exynos-bus";
228 clock-names = "bus";
229 operating-points-v2 = <&bus_leftbus_opp_table>;
234 compatible = "samsung,exynos-bus";
236 clock-names = "bus";
237 operating-points-v2 = <&bus_leftbus_opp_table>;
242 compatible = "samsung,exynos-bus";
244 clock-names = "bus";
245 operating-points-v2 = <&bus_leftbus_opp_table>;
250 compatible = "samsung,exynos-bus";
252 clock-names = "bus";
253 operating-points-v2 = <&bus_leftbus_opp_table>;
258 compatible = "samsung,exynos-bus";
260 clock-names = "bus";
261 operating-points-v2 = <&bus_mcuisp_opp_table>;
266 compatible = "samsung,exynos-bus";
268 clock-names = "bus";
269 operating-points-v2 = <&bus_isp_opp_table>;
274 compatible = "samsung,exynos-bus";
276 clock-names = "bus";
277 operating-points-v2 = <&bus_peril_opp_table>;
282 compatible = "samsung,exynos-bus";
284 clock-names = "bus";
285 operating-points-v2 = <&bus_leftbus_opp_table>;
290 compatible = "operating-points-v2";
291 opp-shared;
293 opp-50000000 {
294 opp-hz = /bits/ 64 <50000000>;
295 opp-microvolt = <900000>;
297 opp-80000000 {
298 opp-hz = /bits/ 64 <80000000>;
299 opp-microvolt = <900000>;
301 opp-100000000 {
302 opp-hz = /bits/ 64 <100000000>;
303 opp-microvolt = <1000000>;
305 opp-134000000 {
306 opp-hz = /bits/ 64 <134000000>;
307 opp-microvolt = <1000000>;
309 opp-200000000 {
310 opp-hz = /bits/ 64 <200000000>;
311 opp-microvolt = <1000000>;
316 compatible = "operating-points-v2";
317 opp-shared;
319 opp-50000000 {
320 opp-hz = /bits/ 64 <50000000>;
322 opp-80000000 {
323 opp-hz = /bits/ 64 <80000000>;
325 opp-100000000 {
326 opp-hz = /bits/ 64 <100000000>;
328 opp-200000000 {
329 opp-hz = /bits/ 64 <200000000>;
331 opp-400000000 {
332 opp-hz = /bits/ 64 <400000000>;
337 compatible = "operating-points-v2";
338 opp-shared;
340 opp-50000000 {
341 opp-hz = /bits/ 64 <50000000>;
343 opp-80000000 {
344 opp-hz = /bits/ 64 <80000000>;
346 opp-100000000 {
347 opp-hz = /bits/ 64 <100000000>;
349 opp-200000000 {
350 opp-hz = /bits/ 64 <200000000>;
352 opp-300000000 {
353 opp-hz = /bits/ 64 <300000000>;
358 compatible = "operating-points-v2";
359 opp-shared;
361 opp-50000000 {
362 opp-hz = /bits/ 64 <50000000>;
364 opp-80000000 {
365 opp-hz = /bits/ 64 <80000000>;
367 opp-100000000 {
368 opp-hz = /bits/ 64 <100000000>;
374 in exynos3250-rinato.dts is listed below:
377 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
378 vdd-supply = <&buck1_reg>; /* VDD_MIF */
383 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
384 vdd-supply = <&buck3_reg>;