Lines Matching full:definition

57       Definition: Must include "fsl,sec-v4.0"
62       Definition: A standard property. Define the 'ERA' of the SEC
68        Definition: A standard property.  Defines the number of cells
74        Definition: A standard property.  Defines the number of cells
81       Definition: A standard property.  Specifies the physical
88        Definition: A standard property.  Specifies the physical address
96       Definition:  Specifies the interrupts generated by this
105       Definition:  A list of phandle and clock specifier pairs describing
111       Definition: A list of clock name strings in the same order as the
168       Definition: Must include "fsl,sec-v4.0-job-ring"
173       Definition: Specifies a two JR parameters:  an offset from
179        Definition:
189       Definition:  Specifies the interrupts generated by this
213   triggered (see SNVS definition).
219       Definition: Must include "fsl,sec-v4.0-rtic".
224        Definition: A standard property.  Defines the number of cells
231        Definition: A standard property.  Defines the number of cells
238       Definition: A standard property.  Specifies a two parameters:
245        Definition: A standard property.  Specifies the physical address
270       Definition: Must include "fsl,sec-v4.0-rtic-memory".
275       Definition: A standard property.  Specifies two parameters:
284        Definition:
293        Definition:
320       Definition: Must include "fsl,sec-v4.0-mon" and "syscon".
325       Definition: A standard property.  Specifies the physical
332        Definition: A standard property.  Defines the number of cells
339        Definition: A standard property.  Defines the number of cells
346        Definition: A standard property.  Specifies the physical address
353       Definition:  Specifies the interrupts generated by this
376       Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
381       Definition: Specifies the interrupts generated by this
390 	Definition: this is phandle to the register map node.
395 	Definition: LP register offset. default it is 0x34.
401       Definition:  a clock specifier describing the clock required for
408       Definition: clock name string should be "snvs-rtc".
430       Definition: Mush include "fsl,sec-v4.0-pwrkey".
435       Definition: The SNVS ON/OFF interrupt number to the CPU(s).
440       Definition: Keycode to emit, KEY_POWER by default.
445       Definition: Button can wake-up the system.
450       Definition: this is phandle to the register map node.