Lines Matching +full:zynqmp +full:- +full:firmware

1 --------------------------------------------------------------------------
3 Zynq MPSoC firmware interface
4 --------------------------------------------------------------------------
12  - #clock-cells:	Must be 1
13  - compatible:		Must contain:	"xlnx,zynqmp-clk"
14  - clocks:		List of clock specifiers which are external input
18  - clock-names:		List of clock names which are exteral input clocks
22 Input clocks for zynqmp Ultrascale+ clock controller:
26  - pss_ref_clk (PS reference clock)
27  - video_clk (reference clock for video system )
28  - pss_alt_ref_clk (alternative PS reference clock)
29  - aux_ref_clk
30  - gt_crx_ref_clk (transceiver reference clock)
32 The following strings are optional parameters to the 'clock-names' property in
34  - swdt0_ext_clk
35  - swdt1_ext_clk
36  - gem0_emio_clk
37  - gem1_emio_clk
38  - gem2_emio_clk
39  - gem3_emio_clk
40  - mio_clk_XX		# with XX = 00..77
41  - mio_clk_50_or_51	#for the mux clock to gem tsu from 50 or 51
45 from firmware. Output clocks indexes are mentioned in
46 include/dt-bindings/clock/xlnx-zynqmp-clk.h.
48 -------
50 -------
52 firmware {
53 	zynqmp_firmware: zynqmp-firmware {
54 		compatible = "xlnx,zynqmp-firmware";
56 		zynqmp_clk: clock-controller {
57 			#clock-cells = <1>;
58 			compatible = "xlnx,zynqmp-clk";
60 			clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";