Lines Matching +full:pre +full:- +full:determined
6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
25 The device type, speed grade and revision are determined runtime by probing.
34 - compatible: shall be one of the following:
35 "silabs,si5340" - Si5340 A/B/C/D
36 "silabs,si5341" - Si5341 A/B/C/D
37 "silabs,si5342" - Si5342 A/B/C/D
38 "silabs,si5344" - Si5344 A/B/C/D
39 "silabs,si5345" - Si5345 A/B/C/D
40 - reg: i2c device address, usually 0x74
41 - #clock-cells: from common clock binding; shall be set to 2.
44 - clocks: from common clock binding; list of parent clock handles,
47 - clock-names: One of: "xtal", "in0", "in1", "in2"
48 - vdd-supply: Regulator node for VDD
51 - vdda-supply: Regulator node for VDDA
52 - vdds-supply: Regulator node for VDDS
53 - silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
55 example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only
59 - silabs,reprogram: When present, the driver will always assume the device must
60 be initialized, and always performs the soft-reset routine. Since this will
63 - interrupts: Interrupt for INTRb pin.
64 - #address-cells: shall be set to 1.
65 - #size-cells: shall be set to 0.
77 - reg: number of clock output.
80 - vdd-supply: Regulator node for VDD for this output. The driver selects default
81 values for common-mode and amplitude based on the voltage.
82 - silabs,format: Output format, one of:
84 2 = low-power (defaults to HCSL levels)
86 - silabs,common-mode: Manually override output common mode, see [2] for values
87 - silabs,amplitude: Manually override output amplitude, see [2] for values
88 - silabs,synth-master: boolean. If present, this output is allowed to change the
90 - silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH
97 compatible = "fixed-clock";
98 #clock-cells = <0>;
99 clock-frequency = <48000000>;
102 i2c-master-node {
104 si5341: clock-generator@74 {
107 #clock-cells = <2>;
108 #address-cells = <1>;
109 #size-cells = <0>;
111 clock-names = "xtal";
113 silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
114 silabs,pll-m-den = <48>;
120 silabs,common-mode = <3>;
122 silabs,synth-master;
132 silabs,common-mode = <13>;
143 silabs,common-mode = <11>;
149 some-video-node {
151 clock-names = "pixel";
155 assigned-clocks = <&si5341 0 7>, <&si5341 1 3>;
156 assigned-clock-parents = <&si5341 1 3>;
158 assigned-clock-rates = <148500000>, <594000000>;
161 some-audio-node {
162 clock-names = "i2s-clk";
165 * since output 0 is a synth-master, the synth will be automatically set
169 assigned-clocks = <&si5341 0 0>;
170 assigned-clock-parents = <&si5341 1 2>;