Lines Matching +full:dsi +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Multimedia Clock & Reset Controller Binding
10 - Jeffrey Hugo <jhugo@codeaurora.org>
11 - Taniya Das <tdas@codeaurora.org>
20 - qcom,mmcc-apq8064
21 - qcom,mmcc-apq8084
22 - qcom,mmcc-msm8660
23 - qcom,mmcc-msm8960
24 - qcom,mmcc-msm8974
25 - qcom,mmcc-msm8996
26 - qcom,mmcc-msm8998
30 - description: Board XO source
31 - description: Board sleep source
32 - description: Global PLL 0 clock
33 - description: DSI phy instance 0 dsi clock
34 - description: DSI phy instance 0 byte clock
35 - description: DSI phy instance 1 dsi clock
36 - description: DSI phy instance 1 byte clock
37 - description: HDMI phy PLL clock
38 - description: DisplayPort phy PLL vco clock
39 - description: DisplayPort phy PLL link clock
41 clock-names:
43 - const: xo
44 - const: sleep
45 - const: gpll0
46 - const: dsi0dsi
47 - const: dsi0byte
48 - const: dsi1dsi
49 - const: dsi1byte
50 - const: hdmipll
51 - const: dpvco
52 - const: dplink
54 '#clock-cells':
57 '#reset-cells':
60 '#power-domain-cells':
66 protected-clocks:
70 vdd-gfx-supply:
75 - compatible
76 - reg
77 - '#clock-cells'
78 - '#reset-cells'
79 - '#power-domain-cells'
87 const: qcom,mmcc-msm8998
91 - clocks
92 - clock-names
96 - |
97 clock-controller@4000000 {
98 compatible = "qcom,mmcc-msm8960";
100 #clock-cells = <1>;
101 #reset-cells = <1>;
102 #power-domain-cells = <1>;