Lines Matching +full:dp +full:- +full:phy0
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Marek <jonathan@marek.ca>
17 dt-bindings/clock/qcom,dispcc-sm8150.h
18 dt-bindings/clock/qcom,dispcc-sm8250.h
23 - qcom,sm8150-dispcc
24 - qcom,sm8250-dispcc
28 - description: Board XO source
29 - description: Byte clock from DSI PHY0
30 - description: Pixel clock from DSI PHY0
31 - description: Byte clock from DSI PHY1
32 - description: Pixel clock from DSI PHY1
33 - description: Link clock from DP PHY
34 - description: VCO DIV clock from DP PHY
36 clock-names:
38 - const: bi_tcxo
39 - const: dsi0_phy_pll_out_byteclk
40 - const: dsi0_phy_pll_out_dsiclk
41 - const: dsi1_phy_pll_out_byteclk
42 - const: dsi1_phy_pll_out_dsiclk
43 - const: dp_phy_pll_link_clk
44 - const: dp_phy_pll_vco_div_clk
46 '#clock-cells':
49 '#reset-cells':
52 '#power-domain-cells':
59 - compatible
60 - reg
61 - clocks
62 - clock-names
63 - '#clock-cells'
64 - '#reset-cells'
65 - '#power-domain-cells'
70 - |
71 #include <dt-bindings/clock/qcom,rpmh.h>
72 clock-controller@af00000 {
73 compatible = "qcom,sm8250-dispcc";
82 clock-names = "bi_tcxo",
89 #clock-cells = <1>;
90 #reset-cells = <1>;
91 #power-domain-cells = <1>;