Lines Matching refs:Clock

1 * Gated Clock bindings for Marvell EBU SoCs
11 ID	Clock	Peripheral
14 1	pex0_en	PCIe 0 Clock out
15 2	pex1_en	PCIe 1 Clock out
28 ID	Clock		Peripheral
33 5	pex0		PCIe 0 Clock out
34 6	pex1		PCIe 1 Clock out
55 ID	Clock		Peripheral
82 ID	Clock		Peripheral
96 ID	Clock	Peripheral
123 ID	Clock	Peripheral
133 ID	Clock	Peripheral
156 ID	Clock	Peripheral
185 - reg : shall be the register address of the Clock Gating Control register