Lines Matching +full:apb +full:- +full:base

5 a base clock and itself is one of the inputs to the two Clock
13 corresponds to one of the base clocks for the LPC18xx.
15  - Above text taken from NXP LPC1850 User Manual.
19     Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - compatible:
23 	Should be "nxp,lpc1850-cgu"
24 - reg:
25 	Shall define the base and range of the address space
27 - #clock-cells:
28 	Shall have value <1>.  The permitted clock-specifier values
29 	are the base clock numbers defined below.
30 - clocks:
34 - clock-indices:
35 	Shall be an ordered list of numbers defining the base clock
37 - clock-output-names:
41 Which base clocks that are available on the CGU depends on the
42 specific LPC part. Base clocks are numbered from 0 to 27.
45  0		BASE_SAFE_CLK		Base safe clock (always on) for WWDT
46  1		BASE_USB0_CLK		Base clock for USB0
47  2		BASE_PERIPH_CLK		Base clock for Cortex-M0SUB subsystem,
49  3		BASE_USB1_CLK		Base clock for USB1
50  4		BASE_CPU_CLK		System base clock for ARM Cortex-M core
51 					and APB peripheral blocks #0 and #2
52  5		BASE_SPIFI_CLK		Base clock for SPIFI
53  6		BASE_SPI_CLK		Base clock for SPI
54  7		BASE_PHY_RX_CLK		Base clock for Ethernet PHY Receive clock
55  8		BASE_PHY_TX_CLK		Base clock for Ethernet PHY Transmit clock
56  9		BASE_APB1_CLK		Base clock for APB peripheral block # 1
57 10		BASE_APB3_CLK		Base clock for APB peripheral block # 3
58 11		BASE_LCD_CLK		Base clock for LCD
59 12		BASE_ADCHS_CLK		Base clock for ADCHS
60 13		BASE_SDIO_CLK		Base clock for SD/MMC
61 14		BASE_SSP0_CLK		Base clock for SSP0
62 15		BASE_SSP1_CLK		Base clock for SSP1
63 16		BASE_UART0_CLK		Base clock for UART0
64 17		BASE_UART1_CLK		Base clock for UART1
65 18		BASE_UART2_CLK		Base clock for UART2
66 19		BASE_UART3_CLK		Base clock for UART3
67 20		BASE_OUT_CLK		Base clock for CLKOUT pin
68 24-21		-			Reserved
69 25		BASE_AUDIO_CLK		Base clock for audio system (I2S)
70 26 		BASE_CGU_OUT0_CLK	Base clock for CGU_OUT0 clock output
71 27 		BASE_CGU_OUT1_CLK	Base clock for CGU_OUT1 clock output
82 			compatible = "fixed-clock";
83 			#clock-cells = <0>;
84 			clock-frequency = <12000000>;
88 			compatible = "fixed-clock";
89 			#clock-cells = <0>;
90 			clock-frequency = <32768>;
94 			compatible = "fixed-clock";
95 			#clock-cells = <0>;
96 			clock-frequency = <0>;
97 			clock-output-names = "enet_rx_clk";
101 			compatible = "fixed-clock";
102 			#clock-cells = <0>;
103 			clock-frequency = <0>;
104 			clock-output-names = "enet_tx_clk";
108 			compatible = "fixed-clock";
109 			#clock-cells = <0>;
110 			clock-frequency = <0>;
111 			clock-output-names = "gp_clkin";
116 		cgu: clock-controller@40050000 {
117 			compatible = "nxp,lpc1850-cgu";
119 			#clock-cells = <1>;
127 			clock-names = "clcdclk", "apb_pclk";