Lines Matching +full:pex +full:- +full:clk2
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra20-pmc
18 - nvidia,tegra30-pmc
19 - nvidia,tegra114-pmc
20 - nvidia,tegra124-pmc
21 - nvidia,tegra210-pmc
28 clock-names:
30 - const: pclk
31 - const: clk32k_in
40 Must contain an entry for each entry in clock-names.
41 See ../clocks/clocks-bindings.txt for details.
43 '#clock-cells':
51 See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
54 '#interrupt-cells':
60 interrupt-controller: true
62 nvidia,invert-interrupt:
70 nvidia,core-power-req-active-high:
72 description: Core power request active-high.
74 nvidia,sys-clock-req-active-high:
76 description: System clock request active-high.
78 nvidia,combined-power-req:
82 nvidia,cpu-pwr-good-en:
87 nvidia,suspend-mode:
92 Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
93 Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
96 nvidia,cpu-pwr-good-time:
100 nvidia,cpu-pwr-off-time:
104 nvidia,core-pwr-good-time:
105 $ref: /schemas/types.yaml#/definitions/uint32-array
107 <Oscillator-stable-time Power-stable-time>
110 nvidia,core-pwr-off-time:
114 nvidia,lp0-vec:
115 $ref: /schemas/types.yaml#/definitions/uint32-array
120 The AVP (Audio-Video Processor) is an ARM7 processor and
127 i2c-thermtrip:
130 On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
131 hardware-triggered thermal reset will be enabled.
134 nvidia,i2c-controller-id:
142 nvidia,bus-addr:
146 nvidia,reg-addr:
150 nvidia,reg-data:
154 nvidia,pinmux-id:
162 - nvidia,i2c-controller-id
163 - nvidia,bus-addr
164 - nvidia,reg-addr
165 - nvidia,reg-data
174 represents a power-domain on the Tegra SoC that can be power-gated
177 "power-domains" property that is a phandle pointing to corresponding
183 use for each power-gate block inside Tegra.
209 "^[a-z0-9]+$":
218 for controlling a power-gate.
219 See ../clocks/clock-bindings.txt document for more details.
226 for controlling a power-gate.
229 '#power-domain-cells':
234 - clocks
235 - resets
236 - '#power-domain-cells'
241 "^[a-f0-9]+-[a-f0-9]+$":
255 see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
261 hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
265 audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
266 debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
267 hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
268 sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
275 low-power-enable:
279 low-power-disable:
283 power-source:
289 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
293 All of the listed Tegra210 pads except pex-cntrl support power
296 audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
297 sdmmc3, spi, spi-hv, and uart.
300 - pins
305 - compatible
306 - reg
307 - clock-names
308 - clocks
309 - '#clock-cells'
314 "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"]
315 "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"]
316 "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"]
319 - |
321 #include <dt-bindings/clock/tegra210-car.h>
322 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
323 #include <dt-bindings/soc/tegra-pmc.h>
326 compatible = "nvidia,tegra210-pmc";
329 clock-names = "pclk", "clk32k_in";
330 #clock-cells = <1>;
332 nvidia,invert-interrupt;
333 nvidia,suspend-mode = <0>;
334 nvidia,cpu-pwr-good-time = <0>;
335 nvidia,cpu-pwr-off-time = <0>;
336 nvidia,core-pwr-good-time = <4587 3876>;
337 nvidia,core-pwr-off-time = <39065>;
338 nvidia,core-power-req-active-high;
339 nvidia,sys-clock-req-active-high;
346 #power-domain-cells = <0>;
352 #power-domain-cells = <0>;