Lines Matching +full:cache +full:- +full:level

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10   UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11   controller system. All of them have a level 2 cache controller, and some
12   have a level 3 cache controller as well.
15   - Masahiro Yamada <yamada.masahiro@socionext.com>
19     const: socionext,uniphier-system-cache
30       Interrupts can be used to notify the completion of cache operations.
36   cache-unified: true
38   cache-size: true
40   cache-sets: true
42   cache-line-size: true
44   cache-level:
48   next-level-cache: true
51   - $ref: /schemas/cache-controller.yaml#
56   - compatible
57   - reg
58   - interrupts
59   - cache-unified
60   - cache-size
61   - cache-sets
62   - cache-line-size
63   - cache-level
66   - |
68     cache-controller@500c0000 {
69         compatible = "socionext,uniphier-system-cache";
72         cache-unified;
73         cache-size = <0x140000>;
74         cache-sets = <512>;
75         cache-line-size = <128>;
76         cache-level = <2>;
78   - |
80     //   L2 should specify the next level cache by 'next-level-cache'.
81     l2: cache-controller@500c0000 {
82         compatible = "socionext,uniphier-system-cache";
85         cache-unified;
86         cache-size = <0x200000>;
87         cache-sets = <512>;
88         cache-line-size = <128>;
89         cache-level = <2>;
90         next-level-cache = <&l3>;
93     l3: cache-controller@500c8000 {
94         compatible = "socionext,uniphier-system-cache";
97         cache-unified;
98         cache-size = <0x200000>;
99         cache-sets = <512>;
100         cache-line-size = <256>;
101         cache-level = <3>;