Lines Matching full:pmu
4 $id: http://devicetree.org/schemas/arm/pmu.yaml#
14 ARM cores often have a PMU for counting cpu and cache events like cache misses
15 and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
22 - apm,potenza-pmu
24 - arm,arm1136-pmu
25 - arm,arm1176-pmu
26 - arm,arm11mpcore-pmu
27 - arm,cortex-a5-pmu
28 - arm,cortex-a7-pmu
29 - arm,cortex-a8-pmu
30 - arm,cortex-a9-pmu
31 - arm,cortex-a12-pmu
32 - arm,cortex-a15-pmu
33 - arm,cortex-a17-pmu
34 - arm,cortex-a32-pmu
35 - arm,cortex-a34-pmu
36 - arm,cortex-a35-pmu
37 - arm,cortex-a53-pmu
38 - arm,cortex-a55-pmu
39 - arm,cortex-a57-pmu
40 - arm,cortex-a65-pmu
41 - arm,cortex-a72-pmu
42 - arm,cortex-a73-pmu
43 - arm,cortex-a75-pmu
44 - arm,cortex-a76-pmu
45 - arm,cortex-a77-pmu
46 - arm,neoverse-e1-pmu
47 - arm,neoverse-n1-pmu
48 - brcm,vulcan-pmu
49 - cavium,thunder-pmu
50 - qcom,krait-pmu
51 - qcom,scorpion-pmu
52 - qcom,scorpion-mp-pmu
67 a PMU of this type signalling the PPI listed in the
78 Indicates that this PMU doesn't support the 0xc and 0xd events.
87 which means the PMU may fail to operate unless external