Lines Matching +full:cpu +full:- +full:idle +full:- +full:states

1 QCOM Idle States for cpuidle driver
3 ARM provides idle-state node to define the cpuidle states, as defined in [1].
4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle
5 states. Idle states have different enter/exit latency and residency values.
6 The idle states supported by the QCOM SoC are defined as -
18 hierarchy to enter standby states, when all cpus are idle. An interrupt brings
20 cache hierarchy is also out of standby, and then the cpu is allowed to resume
30 sequence and would wait for interrupt, before restoring the cpu to execution
33 Standalone PC: A cpu can power down and warmboot if there is a sufficient time
34 between the time it enters idle and the next known wake up. SPC mode is used
36 cpu or the system resources. This helps save power only on that core.  The SPM
37 sequence for this idle state is programmed to power down the supply to the
42 kernel. Entering a power down state for the cpu, needs to be done by trapping
44 code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
48 itself in that the cpu acknowledges and permits the SoC to enter deeper sleep
50 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
53 of this low power mode would be considered high even though at a cpu level,
54 this essentially is cpu power down. The SPM in this state also may handshake
58 The idle-state for QCOM SoCs are distinguished by the compatible property of
59 the idle-states device node.
61 The devicetree representation of the idle state should be -
65 - compatible: Must be one of -
66 			"qcom,idle-state-ret",
67 			"qcom,idle-state-spc",
68 			"qcom,idle-state-pc",
69 		and "arm,idle-state".
75 	idle-states {
77 			compatible = "qcom,idle-state-spc", "arm,idle-state";
78 			entry-latency-us = <150>;
79 			exit-latency-us = <200>;
80 			min-residency-us = <2000>;
84 [1]. Documentation/devicetree/bindings/arm/idle-states.yaml