Lines Matching +full:1 +full:- +full:based
2 --------------------------------------------------------------------
4 The System Controller Firmware (SCFW) is a low-level system function
5 which runs on a dedicated Cortex-M core to provide power, clock, and
9 The AP communicates with the SC using a multi-ported MU module found
22 -------------------
23 - compatible: should be "fsl,imx-scu".
24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3",
27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for
28 rx, and 1 optional MU channel for general interrupt.
36 Channel 1 must be "tx1" or "rx1".
42 &lsio_mu1 0 1
45 &lsio_mu1 1 0
46 &lsio_mu1 1 1
47 &lsio_mu1 1 2
48 &lsio_mu1 1 3
63 Client nodes are maintained as children of the relevant IMX-SCU device node.
65 Power domain bindings based on SCU Message Protocol
66 ------------------------------------------------------------
72 - compatible: Should be one of:
73 "fsl,imx8qm-scu-pd",
74 "fsl,imx8qxp-scu-pd"
75 followed by "fsl,scu-pd"
77 - #power-domain-cells: Must be 1. Contains the Resource ID used by
80 include/dt-bindings/firmware/imx/rsrc.h
82 Clock bindings based on SCU Message Protocol
83 ------------------------------------------------------------
85 This binding uses the common clock binding[1].
88 - compatible: Should be one of:
89 "fsl,imx8qm-clock"
90 "fsl,imx8qxp-clock"
91 followed by "fsl,scu-clk"
92 - #clock-cells: Should be 1. Contains the Clock ID value.
93 - clocks: List of clock specifiers, must contain an entry for
94 each required entry in clock-names
95 - clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"
101 include/dt-bindings/clock/imx8qxp-clock.h
103 Pinctrl bindings based on SCU Message Protocol
104 ------------------------------------------------------------
109 - compatible: Should be one of:
110 "fsl,imx8qm-iomuxc",
111 "fsl,imx8qxp-iomuxc",
112 "fsl,imx8dxl-iomuxc".
115 - fsl,pins: Each entry consists of 3 integers which represents
119 <dt-bindings/pinctrl/pads-imx8qm.h>,
120 <dt-bindings/pinctrl/pads-imx8qxp.h>,
121 <dt-bindings/pinctrl/pads-imx8dxl.h>.
123 pull-up on this pin.
128 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
129 [2] Documentation/devicetree/bindings/power/power-domain.yaml
130 [3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
132 RTC bindings based on SCU Message Protocol
133 ------------------------------------------------------------
136 - compatible: should be "fsl,imx8qxp-sc-rtc";
138 OCOTP bindings based on SCU Message Protocol
139 ------------------------------------------------------------
141 - compatible: Should be one of:
142 "fsl,imx8qm-scu-ocotp",
143 "fsl,imx8qxp-scu-ocotp".
144 - #address-cells: Must be 1. Contains byte index
145 - #size-cells: Must be 1. Contains byte length
149 - Data cells of ocotp:
152 Watchdog bindings based on SCU Message Protocol
153 ------------------------------------------------------------
156 - compatible: should be:
157 "fsl,imx8qxp-sc-wdt"
158 followed by "fsl,imx-sc-wdt";
160 - timeout-sec: contains the watchdog timeout in seconds.
162 SCU key bindings based on SCU Message Protocol
163 ------------------------------------------------------------
166 - compatible: should be:
167 "fsl,imx8qxp-sc-key"
168 followed by "fsl,imx-sc-key";
169 - linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml
171 Thermal bindings based on SCU Message Protocol
172 ------------------------------------------------------------
175 - compatible: Should be :
176 "fsl,imx8qxp-sc-thermal"
177 followed by "fsl,imx-sc-thermal";
179 - #thermal-sensor-cells: See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml
183 -------------
190 #mbox-cells = <2>;
195 compatible = "fsl,imx-scu";
196 mbox-names = "tx0", "tx1", "tx2", "tx3",
200 &lsio_mu1 0 1
203 &lsio_mu1 1 0
204 &lsio_mu1 1 1
205 &lsio_mu1 1 2
206 &lsio_mu1 1 3
210 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
211 #clock-cells = <1>;
215 compatible = "fsl,imx8qxp-iomuxc";
226 ocotp: imx8qx-ocotp {
227 compatible = "fsl,imx8qxp-scu-ocotp";
228 #address-cells = <1>;
229 #size-cells = <1>;
236 pd: imx8qx-pd {
237 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
238 #power-domain-cells = <1>;
242 compatible = "fsl,imx8qxp-sc-rtc";
245 scu_key: scu-key {
246 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
251 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
252 timeout-sec = <60>;
255 tsens: thermal-sensor {
256 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
257 #thermal-sensor-cells = <1>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&pinctrl_lpuart0>;
268 clock-names = "per", "ipg";
269 power-domains = <&pd IMX_SC_R_UART_0>;