Lines Matching +full:rk3066 +full:- +full:smp
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
88 - arm,arm710t
89 - arm,arm720t
90 - arm,arm740t
91 - arm,arm7ej-s
92 - arm,arm7tdmi
93 - arm,arm7tdmi-s
94 - arm,arm9es
95 - arm,arm9ej-s
96 - arm,arm920t
97 - arm,arm922t
98 - arm,arm925
99 - arm,arm926e-s
100 - arm,arm926ej-s
101 - arm,arm940t
102 - arm,arm946e-s
103 - arm,arm966e-s
104 - arm,arm968e-s
105 - arm,arm9tdmi
106 - arm,arm1020e
107 - arm,arm1020t
108 - arm,arm1022e
109 - arm,arm1026ej-s
110 - arm,arm1136j-s
111 - arm,arm1136jf-s
112 - arm,arm1156t2-s
113 - arm,arm1156t2f-s
114 - arm,arm1176jzf
115 - arm,arm1176jz-s
116 - arm,arm1176jzf-s
117 - arm,arm11mpcore
118 - arm,armv8 # Only for s/w models
119 - arm,cortex-a5
120 - arm,cortex-a7
121 - arm,cortex-a8
122 - arm,cortex-a9
123 - arm,cortex-a12
124 - arm,cortex-a15
125 - arm,cortex-a17
126 - arm,cortex-a32
127 - arm,cortex-a34
128 - arm,cortex-a35
129 - arm,cortex-a53
130 - arm,cortex-a55
131 - arm,cortex-a57
132 - arm,cortex-a65
133 - arm,cortex-a72
134 - arm,cortex-a73
135 - arm,cortex-a75
136 - arm,cortex-a76
137 - arm,cortex-a77
138 - arm,cortex-m0
139 - arm,cortex-m0+
140 - arm,cortex-m1
141 - arm,cortex-m3
142 - arm,cortex-m4
143 - arm,cortex-r4
144 - arm,cortex-r5
145 - arm,cortex-r7
146 - arm,neoverse-e1
147 - arm,neoverse-n1
148 - brcm,brahma-b15
149 - brcm,brahma-b53
150 - brcm,vulcan
151 - cavium,thunder
152 - cavium,thunder2
153 - faraday,fa526
154 - intel,sa110
155 - intel,sa1100
156 - marvell,feroceon
157 - marvell,mohawk
158 - marvell,pj4a
159 - marvell,pj4b
160 - marvell,sheeva-v5
161 - marvell,sheeva-v7
162 - nvidia,tegra132-denver
163 - nvidia,tegra186-denver
164 - nvidia,tegra194-carmel
165 - qcom,krait
166 - qcom,kryo
167 - qcom,kryo260
168 - qcom,kryo280
169 - qcom,kryo385
170 - qcom,kryo468
171 - qcom,kryo485
172 - qcom,scorpion
174 enable-method:
177 # On ARM v8 64-bit this property is required
178 - enum:
179 - psci
180 - spin-table
181 # On ARM 32-bit systems this property is optional
182 - enum:
183 - actions,s500-smp
184 - allwinner,sun6i-a31
185 - allwinner,sun8i-a23
186 - allwinner,sun9i-a80-smp
187 - allwinner,sun8i-a83t-smp
188 - amlogic,meson8-smp
189 - amlogic,meson8b-smp
190 - arm,realview-smp
191 - aspeed,ast2600-smp
192 - brcm,bcm11351-cpu-method
193 - brcm,bcm23550
194 - brcm,bcm2836-smp
195 - brcm,bcm63138
196 - brcm,bcm-nsp-smp
197 - brcm,brahma-b15
198 - marvell,armada-375-smp
199 - marvell,armada-380-smp
200 - marvell,armada-390-smp
201 - marvell,armada-xp-smp
202 - marvell,98dx3236-smp
203 - marvell,mmp3-smp
204 - mediatek,mt6589-smp
205 - mediatek,mt81xx-tz-smp
206 - qcom,gcc-msm8660
207 - qcom,kpss-acc-v1
208 - qcom,kpss-acc-v2
209 - renesas,apmu
210 - renesas,r9a06g032-smp
211 - rockchip,rk3036-smp
212 - rockchip,rk3066-smp
213 - socionext,milbeaut-m10v-smp
214 - ste,dbx500-smp
215 - ti,am3352
216 - ti,am4372
218 cpu-release-addr:
222 Required for systems that have an "enable-method"
223 property value of "spin-table".
224 On ARM v8 64-bit systems must be a two cell
225 property identifying a 64-bit zero-initialised
228 cpu-idle-states:
229 $ref: '/schemas/types.yaml#/definitions/phandle-array'
232 by this cpu (see ./idle-states.yaml).
234 capacity-dmips-mhz:
237 u32 value representing CPU capacity (see ./cpu-capacity.txt) in
238 DMIPS/MHz, relative to highest capacity-dmips-mhz
241 dynamic-power-coefficient:
252 calculate the dynamic power as below -
254 Pdyn = dynamic-power-coefficient * V^2 * f
258 power-domains:
259 $ref: '/schemas/types.yaml#/definitions/phandle-array'
264 power-domain-names:
265 $ref: '/schemas/types.yaml#/definitions/string-array'
268 power-domains property.
278 Required for systems that have an "enable-method" property
279 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
288 Required for systems that have an "enable-method" property
289 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
291 * arm/msm/qcom,kpss-acc.txt
298 Optional for systems that have an "enable-method"
299 property value of "rockchip,rk3066-smp"
301 the cpu-core power-domains.
303 secondary-boot-reg:
306 Required for systems that have an "enable-method" property value of
307 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
313 The secondary-boot-reg property is a u32 value that specifies the
320 # If the enable-method property contains one of those values
322 enable-method:
325 - brcm,bcm11351-cpu-method
326 - brcm,bcm23550
327 - brcm,bcm-nsp-smp
328 # and if enable-method is present
330 - enable-method
334 - secondary-boot-reg
337 - device_type
338 - reg
339 - compatible
342 rockchip,pmu: [enable-method]
347 - |
349 #size-cells = <0>;
350 #address-cells = <1>;
354 compatible = "arm,cortex-a15";
360 compatible = "arm,cortex-a15";
366 compatible = "arm,cortex-a7";
372 compatible = "arm,cortex-a7";
377 - |
378 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
380 #size-cells = <0>;
381 #address-cells = <1>;
385 compatible = "arm,cortex-a8";
390 - |
391 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
393 #size-cells = <0>;
394 #address-cells = <1>;
398 compatible = "arm,arm926ej-s";
403 - |
404 // Example 4 (ARM Cortex-A57 64-bit system):
406 #size-cells = <0>;
407 #address-cells = <2>;
411 compatible = "arm,cortex-a57";
413 enable-method = "spin-table";
414 cpu-release-addr = <0 0x20000000>;
419 compatible = "arm,cortex-a57";
421 enable-method = "spin-table";
422 cpu-release-addr = <0 0x20000000>;
427 compatible = "arm,cortex-a57";
429 enable-method = "spin-table";
430 cpu-release-addr = <0 0x20000000>;
435 compatible = "arm,cortex-a57";
437 enable-method = "spin-table";
438 cpu-release-addr = <0 0x20000000>;
443 compatible = "arm,cortex-a57";
445 enable-method = "spin-table";
446 cpu-release-addr = <0 0x20000000>;
451 compatible = "arm,cortex-a57";
453 enable-method = "spin-table";
454 cpu-release-addr = <0 0x20000000>;
459 compatible = "arm,cortex-a57";
461 enable-method = "spin-table";
462 cpu-release-addr = <0 0x20000000>;
467 compatible = "arm,cortex-a57";
469 enable-method = "spin-table";
470 cpu-release-addr = <0 0x20000000>;
475 compatible = "arm,cortex-a57";
477 enable-method = "spin-table";
478 cpu-release-addr = <0 0x20000000>;
483 compatible = "arm,cortex-a57";
485 enable-method = "spin-table";
486 cpu-release-addr = <0 0x20000000>;
491 compatible = "arm,cortex-a57";
493 enable-method = "spin-table";
494 cpu-release-addr = <0 0x20000000>;
499 compatible = "arm,cortex-a57";
501 enable-method = "spin-table";
502 cpu-release-addr = <0 0x20000000>;
507 compatible = "arm,cortex-a57";
509 enable-method = "spin-table";
510 cpu-release-addr = <0 0x20000000>;
515 compatible = "arm,cortex-a57";
517 enable-method = "spin-table";
518 cpu-release-addr = <0 0x20000000>;
523 compatible = "arm,cortex-a57";
525 enable-method = "spin-table";
526 cpu-release-addr = <0 0x20000000>;
531 compatible = "arm,cortex-a57";
533 enable-method = "spin-table";
534 cpu-release-addr = <0 0x20000000>;