Lines Matching +full:0 +full:- +full:127
21 -----------
24 tracked per-thread.
28 instructions and registers, and the Linux-specific system interfaces
54 cpu-feature-registers.txt for details.
63 an endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] encoded at
68 Beware that on big-endian systems this results in a different byte order than
69 for the FPSIMD V-registers, which are stored as single host-endian 128-bit
70 values, with bits [(127 - 8 * i) : (120 - 8 * i)] of the register encoded at
75 -----------------------------
82 * Vector length (VL) = size of a Z-register in bytes
84 * Vector quadwords (VQ) = size of a Z-register in units of 128 bits
90 is used. This is consistent with the meaning of the "VL" pseudo-register in
95 -------------------------
97 * On syscall, V0..V31 are preserved (as without SVE). Thus, bits [127:0] of
106 assumptions about this. The kernel behaviour may vary on a case-by-case
120 -------------------
137 * If the registers are present, the remainder of the record has a vl-dependent
141 * Each scalable register (Zn, Pn, FFR) is stored in an endianness-invariant
152 -----------------
158 then the SVE registers/bits become non-live and take unspecified values.
162 data. However, for backward compatibility reasons, bits [127:0] of Z0..Z31
175 --------------------
238 Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become
248 The following flag may be OR-ed into the result:
266 ---------------------
305 non-live (SETREGSET).
327 ... OR-ed with zero or more of the following flags, which have the same
362 ---------------------------
371 --------------------------------
410 ARMv8-A programmer's model that are relevant to this document.
416 ---------------
420 * 32 8VL-bit vector registers Z0..Z31
421 For each Zn, Zn bits [127:0] alias the ARMv8-A vector register Vn.
424 Zn except for bits [127:0].
426 * 16 VL-bit predicate registers P0..P15
428 * 1 VL-bit special-purpose predicate register FFR (the "first-fault register")
430 * a VL "pseudo-register" that determines the size of each vector register
445 * FPSR and FPCR are retained from ARMv8-A, and interact with SVE floating-point
447 floating-point operations::
449 8VL-1 128 0 bit index
450 +---- //// -----------------+
460 +---- //// -----------------+
461 31 0
462 VL-1 0 +-------+
463 +---- //// --+ FPSR | |
464 P0 | | +-------+
466 P15 | | +-------+
467 +---- //// --+
468 FFR | | +-----+
469 +---- //// --+ VL | |
470 +-----+
472 (*) callee-save:
473 This only applies to bits [63:0] of Z-/V-registers.
474 FPCR contains callee-save and caller-save bits. See [4] for details.
478 -----------------------------
480 The ARMv8-A base procedure call standard is extended as follows with respect to
483 * All SVE register bits that are not shared with FP/SIMD are caller-save.
485 * Z8 bits [63:0] .. Z15 bits [63:0] are callee-save.
487 This follows from the way these bits are mapped to V8..V15, which are caller-
491 Appendix B. ARMv8-A FP/SIMD programmer's model
499 ARMv8-A defines the following floating-point / SIMD register state:
501 * 32 128-bit vector registers V0..V31
502 * 2 32-bit status/control registers FPSR, FPCR
506 127 0 bit index
507 +---------------+
517 +---------------+
519 31 0
520 +-------+
522 +-------+
524 +-------+
526 (*) callee-save:
527 This only applies to bits [63:0] of V-registers.
528 FPCR contains a mixture of callee-save and caller-save bits.
540 [3] Documentation/arm64/cpu-feature-registers.rst
545 Procedure Call Standard for the ARM 64-bit Architecture (AArch64)