Lines Matching full:be
20 hypervisor code, or it may just be a handful of instructions for
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
51 not exceed 2 megabytes in size. Since the dtb will be mapped cacheable
52 using blocks of up to 2 megabytes in size, it must not be placed within
53 any 2M region which must be mapped with any specific attributes.
55 NOTE: versions prior to v4.2 also require that the DTB be placed within
64 therefore requires decompression (gzip etc.) to be performed by the boot
103 little-endian and must be respected. Where image_size is zero,
104 text_offset can be assumed to be 0x80000.
110 Bit 0 Kernel endianness. 1 if BE, 0 if LE.
120 2MB aligned base should be as close as possible
124 2MB aligned base may be anywhere in physical
134 The Image must be placed text_offset bytes from a 2MB aligned base
137 special significance to the kernel, and may be used for other purposes.
138 At least image_size bytes from the start of the image must be free for
141 physical offset of the Image so it is recommended that the Image be
150 memreserve region in the device tree) will be considered as available to
153 Before jumping into the kernel, the following conditions must be met:
168 All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
170 The CPU must be in either EL2 (RECOMMENDED in order to have access to
175 The MMU must be off.
177 The instruction cache may be on or off, and must not hold any stale
180 The address range corresponding to the loaded kernel image must be
185 operations must be configured and may be enabled.
187 operations (not recommended) must be configured and disabled.
191 CNTFRQ must be programmed with the timer frequency and CNTVOFF must
192 be programmed with a consistent value on all CPUs. If entering the
198 All CPUs to be booted by the kernel must be part of the same coherency
206 the kernel image will be entered must be initialised by software at a
211 - The value of SCR_EL3.FIQ must be the same as the one present at boot
214 For systems with a GICv3 interrupt controller to be used in v3 mode:
217 - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
218 - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
219 - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
225 - ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
226 - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
230 For systems with a GICv3 interrupt controller to be used in
235 ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
239 ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
247 - SCR_EL3.APK (bit 16) must be initialised to 0b1
248 - SCR_EL3.API (bit 17) must be initialised to 0b1
252 - HCR_EL2.APK (bit 40) must be initialised to 0b1
253 - HCR_EL2.API (bit 41) must be initialised to 0b1
259 - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
260 - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
261 - AMCNTENSET0_EL0 must be initialised to 0b1111
262 - AMCNTENSET1_EL0 must be initialised to a platform specific value
268 - AMCNTENSET0_EL0 must be initialised to 0b1111
269 - AMCNTENSET1_EL0 must be initialised to a platform specific value
294 device tree) polling their cpu-release-addr location, which must be
295 contained in the reserved region. A wfe instruction may be inserted
296 to reduce the overhead of the busy-loop and a sev will be issued by
299 value. The value will be written as a single 64-bit little-endian