Lines Matching refs:IRQ
16 Secondly, the IRQ subsystem.
39 SA1111 IRQ handler, SA1111 IRQs can hold off SMC9196 IRQs indefinitely.
48 We also bring the idea of an IRQ "chip" (mainly to reduce the size of
57 * Acknowledge the IRQ.
58 * If this is a level-based IRQ, then it is expected to mask the IRQ
63 * Mask the IRQ in hardware.
67 * Unmask the IRQ in hardware.
71 * Re-run the IRQ
75 * Set the type of the IRQ.
90 the hardware IRQ if possible. If not, may call the handler
93 - optional. If you don't support changing the type of an IRQ,
95 set the IRQ type.
97 For each IRQ, we keep the following information:
100 - flags indicating what we can do with this IRQ (valid, probe,
102 - status of the IRQ (probing, enable, etc)
104 - per-IRQ handler
111 "edge" knows about the brokenness of such IRQ implementations - that you
112 need to leave the hardware IRQ enabled while processing it, and queueing
113 further IRQ events should the IRQ happen again while processing. The
129 Set the mask/unmask methods for handling this IRQ
132 Set the handler for this IRQ (level, edge, simple)
135 Set a "chained" handler for this IRQ - automatically
136 enables this IRQ (eg, Neponset and SA1111 handlers).
142 Set active the IRQ edge(s)/level. This replaces the
152 parent IRQ via the correct chip specific function. For instance, if
154 acknowledge the SA1110 IRQ each time you re-read the SA1111 IRQ status.
156 6. For any child which doesn't have its own IRQ enable/disable controls
157 (eg, SMC9196), the handler must mask or acknowledge the parent IRQ
160 the parent IRQ should be unmasked, and the status of all children must
161 be re-checked for pending events. (see the Neponset IRQ handler for
169 solution can't provide the full answer to low IRQ latency.