Lines Matching +full:cpu +full:- +full:idle +full:- +full:states

1 .. SPDX-License-Identifier: GPL-2.0
5 ``intel_idle`` CPU Idle Time Management Driver
17 :doc:`CPU idle time management subsystem <cpuidle>` in the Linux kernel
18 (``CPUIdle``).  It is the default CPU idle time management driver for the
27 logical CPU executing it is idle and so it may be possible to put some of the
28 processor's functional blocks into low-power states.  That instruction takes two
29 arguments (passed in the ``EAX`` and ``ECX`` registers of the target CPU), the
38 only way to pass early-configuration-time parameters to it is via the kernel
42 .. _intel-idle-enumeration-of-states:
44 Enumeration of Idle States
50 as C-states (in the ACPI terminology) or idle states.  The list of meaningful
51 ``MWAIT`` hint values and idle states (i.e. low-power configurations of the
55 In order to create a list of available idle states required by the ``CPUIdle``
56 subsystem (see :ref:`idle-states-representation` in :doc:`cpuidle`),
57 ``intel_idle`` can use two sources of information: static tables of idle states
65 `below <intel-idle-parameters_>`_.]
67 If the ACPI tables are going to be used for building the list of available idle
68 states, ``intel_idle`` first looks for a ``_CST`` object under one of the ACPI
71 ``CPUIdle`` subsystem expects that the list of idle states supplied by the
74 driver looks for the first ``_CST`` object returning at least one valid idle
75 state description and such that all of the idle states included in its return
79 applicable to all of the other CPUs in the system and the idle state
80 descriptions extracted from it are stored in a preliminary list of idle states
82 configured to ignore the ACPI tables; see `below <intel-idle-parameters_>`_.]
84 Next, the first (index 0) entry in the list of available idle states is
85 initialized to represent a "polling idle state" (a pseudo-idle state in which
86 the target CPU continuously fetches and executes instructions), and the
87 subsequent (real) idle state entries are populated as follows.
90 (static) table of idle state descriptions for it in the driver.  In that case,
91 the "internal" table is the primary source of information on idle states and the
92 information from it is copied to the final list of available idle states.  If
93 using the ACPI tables for the enumeration of idle states is not required
94 (depending on the processor model), all of the listed idle state are enabled by
96 governors during CPU idle state selection).  Otherwise, some of the listed idle
97 states may not be enabled by default if there are no matching entries in the
98 preliminary list of idle states coming from the ACPI tables.  In that case user
99 space still can enable them later (on a per-CPU basis) with the help of
100 the ``disable`` idle state attribute in ``sysfs`` (see
101 :ref:`idle-states-representation` in :doc:`cpuidle`).  This basically means that
102 the idle states "known" to the driver may not be enabled by default if they have
106 supports ``MWAIT``, the preliminary list of idle states coming from the ACPI
108 ``CPUIdle`` core during driver registration.  For each idle state in that list,
110 entry in the final list of idle states.  The name of the idle state represented
111 by it (to be returned by the ``name`` idle state attribute in ``sysfs``) is
112 "CX_ACPI", where X is the index of that idle state in the final list (note that
115 C1-type idle states the exit latency value is also used as the target residency
116 (for compatibility with the majority of the "internal" tables of idle states for
117 various processor models recognized by ``intel_idle``) and for the other idle
121 All of the idle states in the final list are enabled by default in this case.
124 .. _intel-idle-initialization:
134 driver, which determines the idle states enumeration method (see
135 `above <intel-idle-enumeration-of-states_>`_), and whether or not the processor
142 `below <intel-idle-parameters_>`_), the idle states information provided by the
146 available idle states is created as explained
147 `above <intel-idle-enumeration-of-states_>`_.
150 as the ``CPUIdle`` driver for all CPUs in the system and a CPU online callback
153 CPUs present in the system at that time (each CPU executes its own instance of
154 the callback routine).  That routine registers a ``CPUIdle`` device for the CPU
155 running it (which enables the ``CPUIdle`` subsystem to operate that CPU) and
156 optionally performs some CPU-specific initialization actions that may be
160 .. _intel-idle-parameters:
166 options related to CPU idle time management: ``idle=poll``, ``idle=halt``,
167 and ``idle=nomwait``.  If any of them is present in the kernel command line, the
175 The ``max_cstate`` parameter value is the maximum idle state index in the list
176 of idle states supplied to the ``CPUIdle`` core during the registration of the
177 driver.  It is also the maximum number of regular (non-polling) idle states that
178 can be used by ``intel_idle``, so the enumeration of idle states is terminated
179 after finding that number of usable idle states (the other idle states that
182 ``intel_idle`` from exposing idle states that are regarded as "too deep" for
185 be desirable.  In practice, it is only really necessary to do that if the idle
186 states in question cannot be enabled during system startup, because in the
187 working state of the system the CPU power management quality of service (PM
188 QoS) feature can be used to prevent ``CPUIdle`` from touching those idle states
189 even if they have been enumerated (see :ref:`cpu-pm-qos` in :doc:`cpuidle`).
199 list of idle states to be disabled by default in the form of a bitmask.
202 the indices of idle states to be disabled by default (as reflected by the names
203 of the corresponding idle state directories in ``sysfs``, :file:`state0`,
205 idle state; see :ref:`idle-states-representation` in :doc:`cpuidle`).
207 For example, if ``states_off`` is equal to 3, the driver will disable idle
208 states 0 and 1 by default, and if it is equal to 8, idle state 3 will be
209 disabled by default and so on (bit positions beyond the maximum idle state index
212 The idle states disabled this way can be enabled (on a per-CPU basis) from user
216 .. _intel-idle-core-and-package-idle-states:
218 Core and Package Levels of Idle States
222 least) two levels of idle states (or C-states).  One level, referred to as
223 "core C-states", covers individual cores in the processor, whereas the other
224 level, referred to as "package C-states", covers the entire processor package
228 Some of the ``MWAIT`` hint values allow the processor to use core C-states only
230 to the ``C1`` idle state), but the majority of them give it a license to put
231 the target core (i.e. the core containing the logical CPU executing ``MWAIT``
232 with the given hint value) into a specific core C-state and then (if possible)
233 to enter a specific package C-state at the deeper level.  For example, the
234 ``MWAIT`` hint value representing the ``C3`` idle state allows the processor to
235 put the target core into the low-power state referred to as "core ``C3``" (or
238 representing a deeper idle state), and in addition to that (in the majority of
240 including some non-CPU components such as a GPU or a memory controller) into the
241 low-power state referred to as "package ``C3``" (or ``PC3``), which happens if
244 be required to be in a certain GPU-specific low-power state for ``PC3`` to be
247 As a rule, there is no simple way to make the processor use core C-states only
248 if the conditions for entering the corresponding package C-states are met, so
249 the logical CPU executing ``MWAIT`` with a hint value that is not core-level
251 enter a package C-state.  [That is why the exit latency and target residency
253 tables of idle states in ``intel_idle`` reflect the properties of package
254 C-states.]  If using package C-states is not desirable at all, either
255 :ref:`PM QoS <cpu-pm-qos>` or the ``max_cstate`` module parameter of
256 ``intel_idle`` described `above <intel-idle-parameters_>`_ must be used to
257 restrict the range of permissible idle states to the ones with core-level only
264 .. [1] *Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 2B*,
265 …www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-develo…