275 	struct vgic_vmcr vmcr;  in vgic_mmio_read_vcpuif()  local
278 	vgic_get_vmcr(vcpu, &vmcr);  in vgic_mmio_read_vcpuif()
282 		val = vmcr.grpen0 << GIC_CPU_CTRL_EnableGrp0_SHIFT;  in vgic_mmio_read_vcpuif()
283 		val |= vmcr.grpen1 << GIC_CPU_CTRL_EnableGrp1_SHIFT;  in vgic_mmio_read_vcpuif()
284 		val |= vmcr.ackctl << GIC_CPU_CTRL_AckCtl_SHIFT;  in vgic_mmio_read_vcpuif()
285 		val |= vmcr.fiqen << GIC_CPU_CTRL_FIQEn_SHIFT;  in vgic_mmio_read_vcpuif()
286 		val |= vmcr.cbpr << GIC_CPU_CTRL_CBPR_SHIFT;  in vgic_mmio_read_vcpuif()
287 		val |= vmcr.eoim << GIC_CPU_CTRL_EOImodeNS_SHIFT;  in vgic_mmio_read_vcpuif()
298 		val = (vmcr.pmr & GICV_PMR_PRIORITY_MASK) >>  in vgic_mmio_read_vcpuif()
302 		val = vmcr.bpr;  in vgic_mmio_read_vcpuif()
305 		val = vmcr.abpr;  in vgic_mmio_read_vcpuif()
323 	struct vgic_vmcr vmcr;  in vgic_mmio_write_vcpuif()  local
325 	vgic_get_vmcr(vcpu, &vmcr);  in vgic_mmio_write_vcpuif()
329 		vmcr.grpen0 = !!(val & GIC_CPU_CTRL_EnableGrp0);  in vgic_mmio_write_vcpuif()
330 		vmcr.grpen1 = !!(val & GIC_CPU_CTRL_EnableGrp1);  in vgic_mmio_write_vcpuif()
331 		vmcr.ackctl = !!(val & GIC_CPU_CTRL_AckCtl);  in vgic_mmio_write_vcpuif()
332 		vmcr.fiqen = !!(val & GIC_CPU_CTRL_FIQEn);  in vgic_mmio_write_vcpuif()
333 		vmcr.cbpr = !!(val & GIC_CPU_CTRL_CBPR);  in vgic_mmio_write_vcpuif()
334 		vmcr.eoim = !!(val & GIC_CPU_CTRL_EOImodeNS);  in vgic_mmio_write_vcpuif()
345 		vmcr.pmr = (val << GICV_PMR_PRIORITY_SHIFT) &  in vgic_mmio_write_vcpuif()
349 		vmcr.bpr = val;  in vgic_mmio_write_vcpuif()
352 		vmcr.abpr = val;  in vgic_mmio_write_vcpuif()
356 	vgic_set_vmcr(vcpu, &vmcr);  in vgic_mmio_write_vcpuif()