40 	counter = __vcpu_sys_reg(vcpu, reg);  in kvm_pmu_get_counter_value()
64 	__vcpu_sys_reg(vcpu, reg) += (s64)val - kvm_pmu_get_counter_value(vcpu, select_idx);  in kvm_pmu_set_counter_value()
81 		__vcpu_sys_reg(vcpu, reg) = counter;  in kvm_pmu_stop_counter()
128 	u64 val = __vcpu_sys_reg(vcpu, PMCR_EL0) >> ARMV8_PMU_PMCR_N_SHIFT;  in kvm_pmu_valid_counter_mask()
150 	if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) || !val)  in kvm_pmu_enable_counter()
196 	if ((__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E)) {  in kvm_pmu_overflow_status()
197 		reg = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);  in kvm_pmu_overflow_status()
198 		reg &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);  in kvm_pmu_overflow_status()
199 		reg &= __vcpu_sys_reg(vcpu, PMINTENSET_EL1);  in kvm_pmu_overflow_status()
298 	__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(idx);  in kvm_pmu_perf_overflow()
319 	enable = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);  in kvm_pmu_software_increment()
323 		type = __vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + i)  in kvm_pmu_software_increment()
327 			reg = __vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) + 1;  in kvm_pmu_software_increment()
329 			__vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = reg;  in kvm_pmu_software_increment()
331 				__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(i);  in kvm_pmu_software_increment()
351 		       __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask);  in kvm_pmu_handle_pmcr()
372 	return (__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E) &&  in kvm_pmu_counter_is_enabled()
373 	       (__vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & BIT(select_idx));  in kvm_pmu_counter_is_enabled()