Lines Matching refs:accesses
29 for cachelines with highest contention - highest number of HITM accesses.
159 - sum of all cachelines accesses
162 - cacheline percentage of all Remote/Local HITM accesses
168 Total - all store accesses
169 L1Hit - store accesses that hit L1
170 L1Hit - store accesses that missed L1
173 - count of local and remote DRAM accesses
176 - count of all accesses that missed LLC
179 - sum of all load accesses
190 - % of Remote/Local HITM accesses for given offset within cacheline
193 - % of store accesses that hit/missed L1 for given offset within cacheline
199 - pid of the process responsible for the accesses
202 - tid of the process responsible for the accesses
205 - code address responsible for the accesses
208 - sum of cycles for given accesses - Remote/Local HITM and generic load
227 The 'Node' field displays nodes that accesses given cacheline
259 - overall statistics of memory accesses