Lines Matching refs:store
83 store instruction accessing the same location (we ignore complicating
166 store to buf but before the store to flag. In this case, r1 and r2
188 store to the same memory location, from any CPU.
194 Since r1 = 1, P0 must store 1 to flag before P1 loads 1 from
202 store to the same address.
207 Since an instruction (in this case, P1's store to flag) cannot
316 is concerned only with the store itself -- its value and its address
389 both branches of an "if" statement store the same value to the same
415 from x could be executed after the store to y. Thus, the memory
483 a control dependency from the load to the store.
498 write. In colloquial terms, the load "reads from" the store. We
499 write W ->rf R to indicate that the load R reads from the store W. We
500 further distinguish the cases where the load and the store occur on
505 though it had been written there by an imaginary initial store that
509 read from a single store. It doesn't apply properly in the presence
510 of load-tearing, where a load obtains some of its bits from one store
511 and some of them from another store. Fortunately, use of READ_ONCE()
572 another. The imaginary store which establishes x's initial value
573 comes first in the coherence order; the store which directly
574 overwrites the initial value comes second; the store which overwrites
591 Write-read coherence: If W ->po-loc R, where W is a store and R
592 is a load, then R must read from W or from some other store
596 is a store, then the store which R reads from must come before
600 loads, then either they read from the same store or else the
601 store read by R comes before the store read by R' in the
609 requirement that every store eventually becomes visible to every CPU.)
626 write-write coherence rule: Since the store of 23 comes later in
628 thus must overwrite the store of 17.
641 rule: The READ_ONCE() load comes before the WRITE_ONCE() store in
642 program order, so it must not read from that store but rather from one
661 If r1 = 5 (reading from P0's store) and r2 = 0 (reading from the
662 imaginary store which establishes x's initial value) at the end, this
664 the r2 load in program order, so it must not read from a store that
675 possible for a store to directly or indirectly overwrite itself! And
691 overwritten by a store. In other words, we have R ->fr W when the
693 equivalently, when R reads from a store which comes earlier than W in
715 the load and the store are on the same CPU) and fre (when they are on
740 When CPU C executes a store instruction, it tells the memory subsystem
741 to store a certain value at a certain location. The memory subsystem
742 propagates the store to all the other CPUs as well as to RAM. (As a
743 special case, we say that the store propagates to its own CPU at the
745 store falls in the location's coherence order. In particular, it must
746 arrange for the store to be co-later than (i.e., to overwrite) any
747 other store to the same location which has already propagated to CPU C.
750 whether there are any as-yet unexecuted store instructions, for the
752 uses the value of the po-latest such store as the value obtained by R,
753 and we say that the store's value is forwarded to R. Otherwise, the
756 of the co-latest store to the location in question which has already
760 CPUs have local caches, and propagating a store to a CPU really means
762 time to process the stores that it receives, and a store can't be used
800 execute all po-earlier instructions before the store
801 associated with the fence (e.g., the store part of an
810 For each other CPU C', any store which propagates to C before
813 store associated with the release fence does.
815 Any store which propagates to C before a strong fence is
898 each load between the store that it reads from and the following
899 store. This leaves the relative positions of loads that read from the
900 same store unspecified; let's say they are inserted in program order,
941 occurs in between CPU 1's load and store. To put it another way, the
942 problem is that the position of CPU 0's store in x's coherence order
943 is between the store that CPU 1 reads from and the store that CPU 1
995 store; either a data, address, or control dependency from a load R to
996 a store W will force the CPU to execute R before W. This is very
998 store before it knows what value should be stored (in the case of a
1000 of an address dependency), or whether the store should actually take
1023 store and a second, po-later load reads from that store:
1029 W, because it can forward the value that W will store to R'. But it
1037 (In theory, a CPU might forward a store to a load when it runs across
1044 because it could tell that the store and the second load access the
1050 program order if the second access is a store. Thus, if we have
1057 read request with the value stored by W (or an even later store), in
1071 a load-acquire reads from an earlier store-release. For example:
1078 executed after the store; the store cannot be forwarded to the load.
1084 store cannot be forwarded to the load. On others, including PowerPC
1087 fence. The upshot is that even though the store may be forwarded to
1088 the load, it is still true that any instruction preceding the store
1090 the store will be executed before any instruction following the load.
1125 smp_wmb() forces P0's store to x to propagate to P1 before the store
1133 that the first store is processed by a busy part of the cache while
1134 the second store is processed by an idle part. As a result, the x = 1
1164 its second load, the x = 1 store would already be fully processed by
1192 that W's store must have propagated to R's CPU before R executed;
1206 execute before W, because the decision as to which store overwrites
1218 on CPU C in situations where a store from some other CPU comes after
1242 had executed before its store then the value of the store would have
1245 event, because P1's store came after P0's store in x's coherence
1246 order, and P1's store propagated to P0 before P0's load executed.
1268 then the x = 9 store must have been propagated to P0 before the first
1271 because P1's store overwrote the value read by P0's first load, and
1272 P1's store propagated to P0 before P0's second load executed.
1300 overwritten by P0's store to buf, the fence guarantees that the store
1301 to buf will propagate to P1 before the store to flag does, and the
1302 store to flag propagates to P1 before P1 reads flag.
1306 from flag were executed first, then the buf = 1 store would already
1355 link from P0's store to its load. This is because P0's store gets
1356 overwritten by P1's store since x = 2 at the end (a coe link), the
1357 smp_wmb() ensures that P1's store to x propagates to P2 before the
1358 store to y does (the first fence), the store to y propagates to P2
1359 before P2's load and store execute, P2's smp_store_release()
1361 store to z does (the second fence), and P0's load executes after the
1362 store to z has propagated to P0 (an rfe link).
1379 store is coherence-later than E and propagates to every CPU and to RAM
1385 Consider first the case where E is a store (implying that the sequence
1406 have propagated to E's CPU before E executed. If E was a store, the
1410 request with the value stored by W or an even later store,
1437 load: an fre link from P0's load to P1's store (which overwrites the
1438 value read by P0), and a strong fence between P1's store and its load.
1472 store that propagates to the critical section's CPU before the
1478 store that propagates to the grace period's CPU before the
1505 means that P0's store to x propagated to P1 before P1 called
1507 P1's grace period. On the other hand, r2 = 0 means that P0's store to
1559 grace period and some store propagates to Z's CPU before Z executes
1631 period, and some store propagates to the critical section's CPU before
1645 Let W be the store mentioned above, let Z come before the end of the
1693 If r2 = 0 at the end then P0's store at X overwrites the value that
1698 If r1 = 1 at the end then P1's load at Y reads from P0's store at W,