Lines Matching refs:P1
119 P1()
130 CPU and P1() represents the read() routine running on another. The
132 Thus, P0 stores the data in buf and then sets flag. Meanwhile, P1
151 A memory model will predict what values P1 might obtain for its loads
160 instance, P1 might run entirely before P0 begins, in which case r1 and
161 r2 will both be 0 at the end. Or P0 might run entirely before P1
165 routines run concurrently. One possibility is that P1 runs after P0's
167 will again both be 0. (If P1 had been designed to read buf
194 Since r1 = 1, P0 must store 1 to flag before P1 loads 1 from
197 P1 loads from flag before loading from buf, since CPUs execute
200 P1 must load 0 from buf before P0 stores 1 to it; otherwise r2
207 Since an instruction (in this case, P1's store to flag) cannot
233 P1()
269 X: P1 loads 1 from flag executes before
270 Y: P1 loads 0 from buf executes before
521 P1()
545 P1()
552 If r1 = 0x56781234 (little-endian!) at the end, then P1 must have read
653 P1()
668 READ_ONCE() in P1, on Itanium it sometimes could end up with r1 = 5
1111 P1()
1120 can malfunction on Alpha systems (notice that P1 uses an ordinary load
1125 smp_wmb() forces P0's store to x to propagate to P1 before the store
1126 to ptr does. And since P1 can't execute its second load
1128 first load, the value x = 1 must have propagated to P1 before the
1132 stores do reach P1's local cache in the proper order, it can happen
1135 value may not become available for P1's CPU to read until after the
1145 between P1's two loads when the kernel is compiled for the Alpha
1154 P1()
1163 then we would never get r1 = &x and r2 = 0. By the time P1 executed
1235 P1()
1245 event, because P1's store came after P0's store in x's coherence
1246 order, and P1's store propagated to P0 before P0's load executed.
1261 P1()
1271 because P1's store overwrote the value read by P0's first load, and
1272 P1's store propagated to P0 before P0's second load executed.
1287 P1()
1298 from P1's second load to its first (backwards!). The reason is
1299 similar to the previous examples: The value P1 loads from buf gets
1301 to buf will propagate to P1 before the store to flag does, and the
1302 store to flag propagates to P1 before P1 reads flag.
1305 P1 must execute its second load before the first. Indeed, if the load
1307 have propagated to P1 by the time P1's load from buf executed, so r2
1312 But what if we put an smp_rmb() fence between P1's loads? The fence
1339 P1()
1356 overwritten by P1's store since x = 2 at the end (a coe link), the
1357 smp_wmb() ensures that P1's store to x propagates to P2 before the
1427 P1()
1436 If r0 = 0 at the end then there is a pb link from P0's load to P1's
1437 load: an fre link from P0's load to P1's store (which overwrites the
1438 value read by P0), and a strong fence between P1's store and its load.
1443 Similarly, if r1 = 0 at the end then there is a pb link from P1's load
1494 P1()
1505 means that P0's store to x propagated to P1 before P1 called
1507 P1's grace period. On the other hand, r2 = 0 means that P0's store to
1509 propagate to P1 before the end of the grace period, violating the
1683 P1()
1694 P1's load at Z reads from, so we have Z ->fre X and thus Z ->rcu-link X.
1698 If r1 = 1 at the end then P1's load at Y reads from P0's store at W,
1720 P1()
1746 P0 P1 P2
1764 section in P0 both starts before P1's grace period does and ends
1765 before it does, and the critical section in P2 both starts after P1's
1884 P1()
1895 you it is not, but the model won't mention that this is because P1