Lines Matching refs:SUN4I_I2S_FMT0_REG
38 #define SUN4I_I2S_FMT0_REG 0x04 macro
345 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG, in sun4i_i2s_set_clk_rate()
800 { SUN4I_I2S_FMT0_REG, 0x0000000c },
813 { SUN4I_I2S_FMT0_REG, 0x00000033 },
895 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
896 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
897 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
898 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
900 .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
912 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
913 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
914 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
915 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
917 .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
929 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
930 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
931 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
932 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
934 .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
953 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
954 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
955 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
956 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19),