Lines Matching refs:component
310 static void m98088_eq_band(struct snd_soc_component *component, unsigned int dai, in m98088_eq_band() argument
328 snd_soc_component_write(component, eq_reg++, M98088_BYTE1(coefs[i])); in m98088_eq_band()
329 snd_soc_component_write(component, eq_reg++, M98088_BYTE0(coefs[i])); in m98088_eq_band()
383 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); in max98088_mic1pre_set() local
384 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_mic1pre_set()
388 snd_soc_component_update_bits(component, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK, in max98088_mic1pre_set()
397 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); in max98088_mic1pre_get() local
398 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_mic1pre_get()
407 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); in max98088_mic2pre_set() local
408 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_mic2pre_set()
412 snd_soc_component_update_bits(component, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK, in max98088_mic2pre_set()
421 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); in max98088_mic2pre_get() local
422 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_mic2pre_get()
620 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max98088_mic_event() local
621 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_mic_event()
626 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, in max98088_mic_event()
629 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, in max98088_mic_event()
634 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 0); in max98088_mic_event()
650 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max98088_line_pga() local
651 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_line_pga()
671 snd_soc_component_update_bits(component, w->reg, in max98088_line_pga()
677 snd_soc_component_update_bits(component, w->reg, in max98088_line_pga()
966 struct snd_soc_component *component = dai->component; in max98088_dai1_hw_params() local
967 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_dai1_hw_params()
979 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT, in max98088_dai1_hw_params()
983 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT, in max98088_dai1_hw_params()
990 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0); in max98088_dai1_hw_params()
995 snd_soc_component_update_bits(component, M98088_REG_11_DAI1_CLKMODE, in max98088_dai1_hw_params()
1000 if (snd_soc_component_read32(component, M98088_REG_14_DAI1_FORMAT) in max98088_dai1_hw_params()
1003 dev_err(component->dev, "Invalid system clock frequency\n"); in max98088_dai1_hw_params()
1009 snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI, in max98088_dai1_hw_params()
1011 snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO, in max98088_dai1_hw_params()
1017 snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS, in max98088_dai1_hw_params()
1020 snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS, in max98088_dai1_hw_params()
1023 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, in max98088_dai1_hw_params()
1033 struct snd_soc_component *component = dai->component; in max98088_dai2_hw_params() local
1034 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_dai2_hw_params()
1046 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT, in max98088_dai2_hw_params()
1050 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT, in max98088_dai2_hw_params()
1057 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0); in max98088_dai2_hw_params()
1062 snd_soc_component_update_bits(component, M98088_REG_19_DAI2_CLKMODE, in max98088_dai2_hw_params()
1067 if (snd_soc_component_read32(component, M98088_REG_1C_DAI2_FORMAT) in max98088_dai2_hw_params()
1070 dev_err(component->dev, "Invalid system clock frequency\n"); in max98088_dai2_hw_params()
1076 snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI, in max98088_dai2_hw_params()
1078 snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO, in max98088_dai2_hw_params()
1084 snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS, in max98088_dai2_hw_params()
1087 snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS, in max98088_dai2_hw_params()
1090 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, in max98088_dai2_hw_params()
1099 struct snd_soc_component *component = dai->component; in max98088_dai_set_sysclk() local
1100 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_dai_set_sysclk()
1111 snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x10); in max98088_dai_set_sysclk()
1113 snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x20); in max98088_dai_set_sysclk()
1115 dev_err(component->dev, "Invalid master clock frequency\n"); in max98088_dai_set_sysclk()
1119 if (snd_soc_component_read32(component, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) { in max98088_dai_set_sysclk()
1120 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, in max98088_dai_set_sysclk()
1122 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, in max98088_dai_set_sysclk()
1135 struct snd_soc_component *component = codec_dai->component; in max98088_dai1_set_fmt() local
1136 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_dai1_set_fmt()
1149 snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI, in max98088_dai1_set_fmt()
1151 snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO, in max98088_dai1_set_fmt()
1161 dev_err(component->dev, "Clock mode unsupported"); in max98088_dai1_set_fmt()
1191 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT, in max98088_dai1_set_fmt()
1198 snd_soc_component_write(component, M98088_REG_15_DAI1_CLOCK, reg15val); in max98088_dai1_set_fmt()
1207 struct snd_soc_component *component = codec_dai->component; in max98088_dai2_set_fmt() local
1208 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_dai2_set_fmt()
1220 snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI, in max98088_dai2_set_fmt()
1222 snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO, in max98088_dai2_set_fmt()
1232 dev_err(component->dev, "Clock mode unsupported"); in max98088_dai2_set_fmt()
1262 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT, in max98088_dai2_set_fmt()
1266 snd_soc_component_write(component, M98088_REG_1D_DAI2_CLOCK, in max98088_dai2_set_fmt()
1275 struct snd_soc_component *component = codec_dai->component; in max98088_dai1_digital_mute() local
1283 snd_soc_component_update_bits(component, M98088_REG_2F_LVL_DAI1_PLAY, in max98088_dai1_digital_mute()
1290 struct snd_soc_component *component = codec_dai->component; in max98088_dai2_digital_mute() local
1298 snd_soc_component_update_bits(component, M98088_REG_31_LVL_DAI2_PLAY, in max98088_dai2_digital_mute()
1303 static int max98088_set_bias_level(struct snd_soc_component *component, in max98088_set_bias_level() argument
1306 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_set_bias_level()
1316 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) in max98088_set_bias_level()
1319 snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN, in max98088_set_bias_level()
1324 snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN, in max98088_set_bias_level()
1383 static int max98088_get_channel(struct snd_soc_component *component, const char *name) in max98088_get_channel() argument
1389 dev_err(component->dev, "Bad EQ channel name '%s'\n", name); in max98088_get_channel()
1393 static void max98088_setup_eq1(struct snd_soc_component *component) in max98088_setup_eq1() argument
1395 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_setup_eq1()
1420 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n", in max98088_setup_eq1()
1425 save = snd_soc_component_read32(component, M98088_REG_49_CFG_LEVEL); in max98088_setup_eq1()
1426 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0); in max98088_setup_eq1()
1430 m98088_eq_band(component, 0, 0, coef_set->band1); in max98088_setup_eq1()
1431 m98088_eq_band(component, 0, 1, coef_set->band2); in max98088_setup_eq1()
1432 m98088_eq_band(component, 0, 2, coef_set->band3); in max98088_setup_eq1()
1433 m98088_eq_band(component, 0, 3, coef_set->band4); in max98088_setup_eq1()
1434 m98088_eq_band(component, 0, 4, coef_set->band5); in max98088_setup_eq1()
1437 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save); in max98088_setup_eq1()
1440 static void max98088_setup_eq2(struct snd_soc_component *component) in max98088_setup_eq2() argument
1442 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_setup_eq2()
1467 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n", in max98088_setup_eq2()
1472 save = snd_soc_component_read32(component, M98088_REG_49_CFG_LEVEL); in max98088_setup_eq2()
1473 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0); in max98088_setup_eq2()
1477 m98088_eq_band(component, 1, 0, coef_set->band1); in max98088_setup_eq2()
1478 m98088_eq_band(component, 1, 1, coef_set->band2); in max98088_setup_eq2()
1479 m98088_eq_band(component, 1, 2, coef_set->band3); in max98088_setup_eq2()
1480 m98088_eq_band(component, 1, 3, coef_set->band4); in max98088_setup_eq2()
1481 m98088_eq_band(component, 1, 4, coef_set->band5); in max98088_setup_eq2()
1484 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, in max98088_setup_eq2()
1491 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); in max98088_put_eq_enum() local
1492 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_put_eq_enum()
1494 int channel = max98088_get_channel(component, kcontrol->id.name); in max98088_put_eq_enum()
1510 max98088_setup_eq1(component); in max98088_put_eq_enum()
1513 max98088_setup_eq2(component); in max98088_put_eq_enum()
1523 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); in max98088_get_eq_enum() local
1524 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_get_eq_enum()
1525 int channel = max98088_get_channel(component, kcontrol->id.name); in max98088_get_eq_enum()
1536 static void max98088_handle_eq_pdata(struct snd_soc_component *component) in max98088_handle_eq_pdata() argument
1538 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_handle_eq_pdata()
1591 ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls)); in max98088_handle_eq_pdata()
1593 dev_err(component->dev, "Failed to add EQ control: %d\n", ret); in max98088_handle_eq_pdata()
1596 static void max98088_handle_pdata(struct snd_soc_component *component) in max98088_handle_pdata() argument
1598 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_handle_pdata()
1603 dev_dbg(component->dev, "No platform data\n"); in max98088_handle_pdata()
1616 snd_soc_component_write(component, M98088_REG_48_CFG_MIC, regval); in max98088_handle_pdata()
1620 snd_soc_component_update_bits(component, M98088_REG_2A_MIC_REC_CNTL, in max98088_handle_pdata()
1625 max98088_handle_eq_pdata(component); in max98088_handle_pdata()
1628 static int max98088_probe(struct snd_soc_component *component) in max98088_probe() argument
1630 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_probe()
1658 ret = snd_soc_component_read32(component, M98088_REG_FF_REV_ID); in max98088_probe()
1660 dev_err(component->dev, "Failed to read device revision: %d\n", in max98088_probe()
1664 dev_info(component->dev, "revision %c\n", ret - 0x40 + 'A'); in max98088_probe()
1666 snd_soc_component_write(component, M98088_REG_51_PWR_SYS, M98088_PWRSV); in max98088_probe()
1668 snd_soc_component_write(component, M98088_REG_0F_IRQ_ENABLE, 0x00); in max98088_probe()
1670 snd_soc_component_write(component, M98088_REG_22_MIX_DAC, in max98088_probe()
1674 snd_soc_component_write(component, M98088_REG_4E_BIAS_CNTL, 0xF0); in max98088_probe()
1675 snd_soc_component_write(component, M98088_REG_50_DAC_BIAS2, 0x0F); in max98088_probe()
1677 snd_soc_component_write(component, M98088_REG_16_DAI1_IOCFG, in max98088_probe()
1680 snd_soc_component_write(component, M98088_REG_1E_DAI2_IOCFG, in max98088_probe()
1683 max98088_handle_pdata(component); in max98088_probe()
1689 static void max98088_remove(struct snd_soc_component *component) in max98088_remove() argument
1691 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); in max98088_remove()