Lines Matching refs:dmadscr
217 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; in set_acp_sysmem_dma_descriptors() local
220 dmadscr[i].xfer_val = 0; in set_acp_sysmem_dma_descriptors()
223 dmadscr[i].dest = sram_bank + (i * (size / 2)); in set_acp_sysmem_dma_descriptors()
224 dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS in set_acp_sysmem_dma_descriptors()
228 dmadscr[i].xfer_val |= in set_acp_sysmem_dma_descriptors()
233 dmadscr[i].xfer_val |= in set_acp_sysmem_dma_descriptors()
239 dmadscr[i].src = sram_bank + (i * (size / 2)); in set_acp_sysmem_dma_descriptors()
240 dmadscr[i].dest = in set_acp_sysmem_dma_descriptors()
245 dmadscr[i].xfer_val |= in set_acp_sysmem_dma_descriptors()
250 dmadscr[i].xfer_val |= in set_acp_sysmem_dma_descriptors()
256 &dmadscr[i]); in set_acp_sysmem_dma_descriptors()
275 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; in set_acp_to_i2s_dma_descriptors() local
278 dmadscr[i].xfer_val = 0; in set_acp_to_i2s_dma_descriptors()
281 dmadscr[i].src = sram_bank + (i * (size / 2)); in set_acp_to_i2s_dma_descriptors()
283 dmadscr[i].dest = 0; in set_acp_to_i2s_dma_descriptors()
284 dmadscr[i].xfer_val |= BIT(22) | (destination << 16) | in set_acp_to_i2s_dma_descriptors()
289 dmadscr[i].src = 0; in set_acp_to_i2s_dma_descriptors()
290 dmadscr[i].dest = in set_acp_to_i2s_dma_descriptors()
292 dmadscr[i].xfer_val |= BIT(22) | in set_acp_to_i2s_dma_descriptors()
296 &dmadscr[i]); in set_acp_to_i2s_dma_descriptors()