221 #define BA0_CLKCR1		0x0400	/* Clock Control Register 1 */  macro
1311 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);  in snd_cs4281_free()
1456 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);  in snd_cs4281_chip_init()
1486 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_DLLP);  in snd_cs4281_chip_init()
1488 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, BA0_CLKCR1_SWCE | BA0_CLKCR1_DLLP);  in snd_cs4281_chip_init()
1499 		if (snd_cs4281_peekBA0(chip, BA0_CLKCR1) & BA0_CLKCR1_DLLRDY)  in snd_cs4281_chip_init()
2010 	ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);  in cs4281_suspend()
2012 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);  in cs4281_suspend()
2029 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, 0);  in cs4281_suspend()
2034 	ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);  in cs4281_suspend()
2036 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);  in cs4281_suspend()
2047 	ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);  in cs4281_resume()
2049 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);  in cs4281_resume()
2061 	ulCLK = snd_cs4281_peekBA0(chip, BA0_CLKCR1);  in cs4281_resume()
2063 	snd_cs4281_pokeBA0(chip, BA0_CLKCR1, ulCLK);  in cs4281_resume()