117 #define OPTi9XX_MC_REG(n)	n  macro
352 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(4), 0xf0, 0xfc);  in snd_opti9xx_configure()
354 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(6), 0x02, 0x02);  in snd_opti9xx_configure()
359 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(1), 0x80, 0x80);  in snd_opti9xx_configure()
361 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2), 0x00, 0x20);  in snd_opti9xx_configure()
363 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(3), 0xf0, 0xff);  in snd_opti9xx_configure()
366 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x02, 0x02);  in snd_opti9xx_configure()
369 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x00, 0x02);  in snd_opti9xx_configure()
375 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(1), 0x80, 0x80);  in snd_opti9xx_configure()
376 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2), 0x00, 0x20);  in snd_opti9xx_configure()
380 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(4), 0x00, 0x0c);  in snd_opti9xx_configure()
382 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x02, 0x02);  in snd_opti9xx_configure()
384 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x00, 0x02);  in snd_opti9xx_configure()
391 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(20), 0x04, 0x0c);  in snd_opti9xx_configure()
397 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(21), 0x82, 0xff);  in snd_opti9xx_configure()
402 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(26), 0x01, 0x01);  in snd_opti9xx_configure()
404 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(6), 0x02, 0x03);  in snd_opti9xx_configure()
405 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(3), 0x00, 0xff);  in snd_opti9xx_configure()
406 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(4), 0x10 |  in snd_opti9xx_configure()
409 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(5), 0x20, 0xbf);  in snd_opti9xx_configure()
440 	snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(1), wss_base_bits << 4, 0x30);  in snd_opti9xx_configure()
501 	snd_opti9xx_write(chip, OPTi9XX_MC_REG(3), (irq_bits << 3 | dma_bits));  in snd_opti9xx_configure()
547 		snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(6),  in snd_opti9xx_configure()
655 	status = snd_opti9xx_read(chip, OPTi9XX_MC_REG(11));  in snd_opti93x_interrupt()
680 	value = snd_opti9xx_read(chip, OPTi9XX_MC_REG(1));  in snd_opti9xx_read_check()
681 	if (value != 0xff && value != inb(chip->mc_base + OPTi9XX_MC_REG(1)))  in snd_opti9xx_read_check()
682 		if (value == snd_opti9xx_read(chip, OPTi9XX_MC_REG(1)))  in snd_opti9xx_read_check()
695 	value = snd_opti9xx_read(chip, OPTi9XX_MC_REG(7));  in snd_opti9xx_read_check()
696 	snd_opti9xx_write(chip, OPTi9XX_MC_REG(7), 0xff - value);  in snd_opti9xx_read_check()
697 	if (snd_opti9xx_read(chip, OPTi9XX_MC_REG(7)) == 0xff - value)  in snd_opti9xx_read_check()
914 			snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2),
919 				snd_opti9xx_write_mask(chip, OPTi9XX_MC_REG(2),