Lines Matching refs:__u32
162 __u32 fpga_id; /* FPGA Identification Register */
163 __u32 fpga_version; /* FPGA Version Number Register */
164 __u32 cpu_start; /* CPU start Register (write) */
165 __u32 cpu_stop; /* CPU stop Register (write) */
166 __u32 misc_reg; /* Miscellaneous Register */
167 __u32 idt_mode; /* IDT mode Register */
168 __u32 uart_irq_status; /* UART IRQ status Register */
169 __u32 clear_timer0_irq; /* Clear timer interrupt Register */
170 __u32 clear_timer1_irq; /* Clear timer interrupt Register */
171 __u32 clear_timer2_irq; /* Clear timer interrupt Register */
172 __u32 test_register; /* Test Register */
173 __u32 test_count; /* Test Count Register */
174 __u32 timer_select; /* Timer select register */
175 __u32 pr_uart_irq_status; /* Prioritized UART IRQ stat Reg */
176 __u32 ram_wait_state; /* RAM wait-state Register */
177 __u32 uart_wait_state; /* UART wait-state Register */
178 __u32 timer_wait_state; /* timer wait-state Register */
179 __u32 ack_wait_state; /* ACK wait State Register */
189 __u32 loc_addr_range; /* 00h - Local Address Range */
190 __u32 loc_addr_base; /* 04h - Local Address Base */
191 __u32 loc_arbitr; /* 08h - Local Arbitration */
192 __u32 endian_descr; /* 0Ch - Big/Little Endian Descriptor */
193 __u32 loc_rom_range; /* 10h - Local ROM Range */
194 __u32 loc_rom_base; /* 14h - Local ROM Base */
195 __u32 loc_bus_descr; /* 18h - Local Bus descriptor */
196 __u32 loc_range_mst; /* 1Ch - Local Range for Master to PCI */
197 __u32 loc_base_mst; /* 20h - Local Base for Master PCI */
198 __u32 loc_range_io; /* 24h - Local Range for Master IO */
199 __u32 pci_base_mst; /* 28h - PCI Base for Master PCI */
200 __u32 pci_conf_io; /* 2Ch - PCI configuration for Master IO */
201 __u32 filler1; /* 30h */
202 __u32 filler2; /* 34h */
203 __u32 filler3; /* 38h */
204 __u32 filler4; /* 3Ch */
205 __u32 mail_box_0; /* 40h - Mail Box 0 */
206 __u32 mail_box_1; /* 44h - Mail Box 1 */
207 __u32 mail_box_2; /* 48h - Mail Box 2 */
208 __u32 mail_box_3; /* 4Ch - Mail Box 3 */
209 __u32 filler5; /* 50h */
210 __u32 filler6; /* 54h */
211 __u32 filler7; /* 58h */
212 __u32 filler8; /* 5Ch */
213 __u32 pci_doorbell; /* 60h - PCI to Local Doorbell */
214 __u32 loc_doorbell; /* 64h - Local to PCI Doorbell */
215 __u32 intr_ctrl_stat; /* 68h - Interrupt Control/Status */
216 __u32 init_ctrl; /* 6Ch - EEPROM control, Init Control, etc */
258 __u32 signature; /* ZFIRM/U signature */
259 __u32 zfwctrl_addr; /* pointer to ZFW_CTRL structure */
396 __u32 op_mode; /* operation mode */
397 __u32 intr_enable; /* interrupt masking */
398 __u32 sw_flow; /* SW flow control */
399 __u32 flow_status; /* output flow status */
400 __u32 comm_baud; /* baud rate - numerically specified */
401 __u32 comm_parity; /* parity */
402 __u32 comm_data_l; /* data length/stop */
403 __u32 comm_flags; /* other flags */
404 __u32 hw_flow; /* HW flow control */
405 __u32 rs_control; /* RS-232 outputs */
406 __u32 rs_status; /* RS-232 inputs */
407 __u32 flow_xon; /* xon char */
408 __u32 flow_xoff; /* xoff char */
409 __u32 hw_overflow; /* hw overflow counter */
410 __u32 sw_overflow; /* sw overflow counter */
411 __u32 comm_error; /* frame/parity error counter */
412 __u32 ichar;
413 __u32 filler[7];
423 __u32 flag_dma; /* buffers are in Host memory */
424 __u32 tx_bufaddr; /* address of the tx buffer */
425 __u32 tx_bufsize; /* tx buffer size */
426 __u32 tx_threshold; /* tx low water mark */
427 __u32 tx_get; /* tail index tx buf */
428 __u32 tx_put; /* head index tx buf */
429 __u32 rx_bufaddr; /* address of the rx buffer */
430 __u32 rx_bufsize; /* rx buffer size */
431 __u32 rx_threshold; /* rx high water mark */
432 __u32 rx_get; /* tail index rx buf */
433 __u32 rx_put; /* head index rx buf */
434 __u32 filler[5]; /* filler to align structures */
445 __u32 n_channel; /* number of channels */
446 __u32 fw_version; /* firmware version */
449 __u32 op_system; /* op_system id */
450 __u32 dr_version; /* driver version */
453 __u32 inactivity; /* inactivity control */
456 __u32 hcmd_channel; /* channel number */
457 __u32 hcmd_param; /* pointer to parameters */
460 __u32 fwcmd_channel; /* channel number */
461 __u32 fwcmd_param; /* pointer to parameters */
462 __u32 zf_int_queue_addr; /* offset for INT_QUEUE structure */
465 __u32 filler[6];