Lines Matching refs:fourcc_mod_code
191 #define fourcc_mod_code(vendor, val) \ macro
209 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
219 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
235 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
250 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
265 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
284 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
285 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
300 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
313 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
323 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
335 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
344 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
353 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
362 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
386 fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
389 fourcc_mod_code(NVIDIA, 0x10)
391 fourcc_mod_code(NVIDIA, 0x11)
393 fourcc_mod_code(NVIDIA, 0x12)
395 fourcc_mod_code(NVIDIA, 0x13)
397 fourcc_mod_code(NVIDIA, 0x14)
399 fourcc_mod_code(NVIDIA, 0x15)
410 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
437 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
500 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
513 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode)