101 #define rtsx_pci_writel(pcr, reg, value) \  argument
102 	iowrite32(value, (pcr)->remap_addr + reg)
103 #define rtsx_pci_readl(pcr, reg) \  argument
104 	ioread32((pcr)->remap_addr + reg)
105 #define rtsx_pci_writew(pcr, reg, value) \  argument
106 	iowrite16(value, (pcr)->remap_addr + reg)
107 #define rtsx_pci_readw(pcr, reg) \  argument
108 	ioread16((pcr)->remap_addr + reg)
109 #define rtsx_pci_writeb(pcr, reg, value) \  argument
110 	iowrite8(value, (pcr)->remap_addr + reg)
111 #define rtsx_pci_readb(pcr, reg) \  argument
112 	ioread8((pcr)->remap_addr + reg)
114 #define rtsx_pci_read_config_byte(pcr, where, val) \  argument
115 	pci_read_config_byte((pcr)->pci, where, val)
117 #define rtsx_pci_write_config_byte(pcr, where, val) \  argument
118 	pci_write_config_byte((pcr)->pci, where, val)
120 #define rtsx_pci_read_config_dword(pcr, where, val) \  argument
121 	pci_read_config_dword((pcr)->pci, where, val)
123 #define rtsx_pci_write_config_dword(pcr, where, val) \  argument
124 	pci_write_config_dword((pcr)->pci, where, val)
1064 #define rtsx_pci_init_cmd(pcr)		((pcr)->ci = 0)  argument
1072 	struct rtsx_pcr			*pcr;  member
1076 	int (*write_phy)(struct rtsx_pcr *pcr, u8 addr, u16 val);
1077 	int (*read_phy)(struct rtsx_pcr *pcr, u8 addr, u16 *val);
1078 	int		(*extra_init_hw)(struct rtsx_pcr *pcr);
1079 	int		(*optimize_phy)(struct rtsx_pcr *pcr);
1080 	int		(*turn_on_led)(struct rtsx_pcr *pcr);
1081 	int		(*turn_off_led)(struct rtsx_pcr *pcr);
1082 	int		(*enable_auto_blink)(struct rtsx_pcr *pcr);
1083 	int		(*disable_auto_blink)(struct rtsx_pcr *pcr);
1084 	int		(*card_power_on)(struct rtsx_pcr *pcr, int card);
1085 	int		(*card_power_off)(struct rtsx_pcr *pcr, int card);
1086 	int		(*switch_output_voltage)(struct rtsx_pcr *pcr,
1088 	unsigned int	(*cd_deglitch)(struct rtsx_pcr *pcr);
1090 	void		(*fetch_vendor_settings)(struct rtsx_pcr *pcr);
1091 	void		(*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state);
1092 	void		(*stop_cmd)(struct rtsx_pcr *pcr);
1094 	void (*set_aspm)(struct rtsx_pcr *pcr, bool enable);
1095 	int (*set_ltr_latency)(struct rtsx_pcr *pcr, u32 latency);
1096 	int (*set_l1off_sub)(struct rtsx_pcr *pcr, u8 val);
1097 	void (*set_l1off_cfg_sub_d0)(struct rtsx_pcr *pcr, int active);
1098 	void (*full_on)(struct rtsx_pcr *pcr);
1099 	void (*power_saving)(struct rtsx_pcr *pcr);
1100 	void (*enable_ocp)(struct rtsx_pcr *pcr);
1101 	void (*disable_ocp)(struct rtsx_pcr *pcr);
1102 	void (*init_ocp)(struct rtsx_pcr *pcr);
1103 	void (*process_ocp)(struct rtsx_pcr *pcr);
1104 	int (*get_ocpstat)(struct rtsx_pcr *pcr, u8 *val);
1105 	void (*clear_ocpstat)(struct rtsx_pcr *pcr);
1278 #define CHK_PCI_PID(pcr, pid)		((pcr)->pci->device == (pid))  argument
1279 #define PCI_VID(pcr)			((pcr)->pci->vendor)  argument
1280 #define PCI_PID(pcr)			((pcr)->pci->device)  argument
1281 #define is_version(pcr, pid, ver)				\  argument
1282 	(CHK_PCI_PID(pcr, pid) && (pcr)->ic_version == (ver))
1283 #define pcr_dbg(pcr, fmt, arg...)				\  argument
1284 	dev_dbg(&(pcr)->pci->dev, fmt, ##arg)
1289 #define SDR104_TX_PHASE(pcr)		SDR104_PHASE((pcr)->tx_initial_phase)  argument
1290 #define SDR50_TX_PHASE(pcr)		SDR50_PHASE((pcr)->tx_initial_phase)  argument
1291 #define DDR50_TX_PHASE(pcr)		DDR50_PHASE((pcr)->tx_initial_phase)  argument
1292 #define SDR104_RX_PHASE(pcr)		SDR104_PHASE((pcr)->rx_initial_phase)  argument
1293 #define SDR50_RX_PHASE(pcr)		SDR50_PHASE((pcr)->rx_initial_phase)  argument
1294 #define DDR50_RX_PHASE(pcr)		DDR50_PHASE((pcr)->rx_initial_phase)  argument
1298 void rtsx_pci_start_run(struct rtsx_pcr *pcr);
1299 int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data);
1300 int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data);
1301 int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val);
1302 int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val);
1303 void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr);
1304 void rtsx_pci_add_cmd(struct rtsx_pcr *pcr,
1306 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr);
1307 int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout);
1308 int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1310 int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1312 void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1314 int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist,
1316 int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
1317 int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len);
1318 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card);
1319 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card);
1320 int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock,
1322 int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card);
1323 int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card);
1324 int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card);
1325 int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage);
1326 unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr);
1327 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr);
1329 static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr)  in rtsx_pci_get_cmd_data()  argument
1331 	return (u8 *)(pcr->host_cmds_ptr);  in rtsx_pci_get_cmd_data()
1334 static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr,  in rtsx_pci_update_cfg_byte()  argument
1340 	err = pci_read_config_byte(pcr->pci, addr, &val);  in rtsx_pci_update_cfg_byte()
1343 	return pci_write_config_byte(pcr->pci, addr, (val & mask) | append);  in rtsx_pci_update_cfg_byte()
1346 static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val)  in rtsx_pci_write_be32()  argument
1348 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg,     0xFF, val >> 24);  in rtsx_pci_write_be32()
1349 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16);  in rtsx_pci_write_be32()
1350 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8);  in rtsx_pci_write_be32()
1351 	rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val);  in rtsx_pci_write_be32()
1354 static inline int rtsx_pci_update_phy(struct rtsx_pcr *pcr, u8 addr,  in rtsx_pci_update_phy()  argument
1360 	err = rtsx_pci_read_phy_register(pcr, addr, &val);  in rtsx_pci_update_phy()
1364 	return rtsx_pci_write_phy_register(pcr, addr, (val & mask) | append);  in rtsx_pci_update_phy()