Lines Matching defs:pci_dev
286 struct pci_dev { struct
287 struct list_head bus_list; /* Node in per-bus list */
288 struct pci_bus *bus; /* Bus this device is on */
289 struct pci_bus *subordinate; /* Bus this device bridges to */
291 void *sysdata; /* Hook for sys-specific extension */
292 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
293 struct pci_slot *slot; /* Physical slot this device is in */
295 unsigned int devfn; /* Encoded device & function index */
296 unsigned short vendor;
297 unsigned short device;
298 unsigned short subsystem_vendor;
299 unsigned short subsystem_device;
300 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
301 u8 revision; /* PCI revision, low byte of class word */
302 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
304 u16 aer_cap; /* AER capability offset */
305 struct aer_stats *aer_stats; /* AER stats for this device */
307 u8 pcie_cap; /* PCIe capability offset */
308 u8 msi_cap; /* MSI capability offset */
309 u8 msix_cap; /* MSI-X capability offset */
310 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
311 u8 rom_base_reg; /* Config register controlling ROM */
312 u8 pin; /* Interrupt pin this device uses */
313 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
314 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
316 struct pci_driver *driver; /* Driver bound to this device */
317 u64 dma_mask; /* Mask of the bits of bus address this
323 struct device_dma_parameters dma_parms;
325 pci_power_t current_state; /* Current operating state. In ACPI,
328 u8 pm_cap; /* PM capability offset */
329 unsigned int pme_support:5; /* Bitmask of states from which PME#
331 unsigned int pme_poll:1; /* Poll device's PME status bit */
332 unsigned int d1_support:1; /* Low power state D1 is supported */
333 unsigned int d2_support:1; /* Low power state D2 is supported */
334 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
335 unsigned int no_d3cold:1; /* D3cold is forbidden */
336 unsigned int bridge_d3:1; /* Allow D3 for bridge */
337 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
338 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
340 unsigned int wakeup_prepared:1;
341 unsigned int runtime_d3cold:1; /* Whether go through runtime
345 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
346 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
349 unsigned int d3_delay; /* D3->D0 transition time in ms */
350 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
353 struct pcie_link_state *link_state; /* ASPM link state */
354 unsigned int ltr_path:1; /* Latency Tolerance Reporting
357 unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
359 pci_channel_state_t error_state; /* Current connectivity state */
360 struct device dev; /* Generic device interface */
362 int cfg_size; /* Size of config space */
368 unsigned int irq;
369 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
371 bool match_driver; /* Skip attaching driver */
373 unsigned int transparent:1; /* Subtractive decode bridge */
374 unsigned int multifunction:1; /* Multi-function device */
376 unsigned int is_busmaster:1; /* Is busmaster */
377 unsigned int no_msi:1; /* May not use MSI */
378 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
379 unsigned int block_cfg_access:1; /* Config space access blocked */
380 unsigned int broken_parity_status:1; /* Generates false positive parity */
381 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
405 pci_dev_flags_t dev_flags; argument
406 atomic_t enable_cnt; /* pci_enable_device has been called */
430 struct pci_dev *physfn; /* VF: related PF */ argument
449 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) in pci_physfn() argument
624 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) in pci_dev_msi_enabled()
629 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } in pci_dev_msi_enabled()