1078 #define MLX5_CAP_GEN(mdev, cap) \  argument
1079 	MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1081 #define MLX5_CAP_GEN_64(mdev, cap) \  argument
1082 	MLX5_GET64(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1084 #define MLX5_CAP_GEN_MAX(mdev, cap) \  argument
1085 	MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
1087 #define MLX5_CAP_ETH(mdev, cap) \  argument
1089 		 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1091 #define MLX5_CAP_ETH_MAX(mdev, cap) \  argument
1093 		 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1095 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \  argument
1097 		 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap)
1099 #define MLX5_CAP_ROCE(mdev, cap) \  argument
1100 	MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
1102 #define MLX5_CAP_ROCE_MAX(mdev, cap) \  argument
1103 	MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
1105 #define MLX5_CAP_ATOMIC(mdev, cap) \  argument
1106 	MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
1108 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \  argument
1109 	MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
1111 #define MLX5_CAP_FLOWTABLE(mdev, cap) \  argument
1112 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1114 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \  argument
1115 	MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
1117 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \  argument
1118 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1120 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \  argument
1121 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1123 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \  argument
1124 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1126 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \  argument
1127 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1129 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \  argument
1130 	MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1132 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \  argument
1133 	MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1135 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \  argument
1137 		 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1139 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \  argument
1141 		 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1143 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \  argument
1144 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1146 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \  argument
1147 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1149 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \  argument
1150 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1152 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \  argument
1153 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1155 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \  argument
1156 	MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1158 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \  argument
1159 	MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1161 #define MLX5_CAP_ESW(mdev, cap) \  argument
1163 		 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
1165 #define MLX5_CAP_ESW_MAX(mdev, cap) \  argument
1167 		 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
1169 #define MLX5_CAP_ODP(mdev, cap)\  argument
1170 	MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
1172 #define MLX5_CAP_VECTOR_CALC(mdev, cap) \  argument
1174 		 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
1176 #define MLX5_CAP_QOS(mdev, cap)\  argument
1177 	MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1179 #define MLX5_CAP_DEBUG(mdev, cap)\  argument
1180 	MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap)
1200 #define MLX5_CAP_FPGA(mdev, cap) \  argument
1201 	MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1203 #define MLX5_CAP64_FPGA(mdev, cap) \  argument
1204 	MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1206 #define MLX5_CAP_DEV_MEM(mdev, cap)\  argument
1207 	MLX5_GET(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1209 #define MLX5_CAP64_DEV_MEM(mdev, cap)\  argument
1210 	MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)