Lines Matching refs:BIT
98 #define LP87565_BUCK_CTRL_1_EN BIT(7)
99 #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6)
102 #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3)
103 #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2)
104 #define LP87565_BUCK_CTRL_1_FPWM BIT(1)
106 #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0)
120 #define LP87565_RESET_SW_RESET BIT(0)
122 #define LP87565_CONFIG_DOUBLE_DELAY BIT(7)
123 #define LP87565_CONFIG_CLKIN_PD BIT(6)
124 #define LP87565_CONFIG_EN4_PD BIT(5)
125 #define LP87565_CONFIG_EN3_PD BIT(4)
126 #define LP87565_CONFIG_TDIE_WARN_LEVEL BIT(3)
127 #define LP87565_CONFIG_EN2_PD BIT(2)
128 #define LP87565_CONFIG_EN1_PD BIT(1)
130 #define LP87565_INT_GPIO BIT(7)
131 #define LP87565_INT_BUCK23 BIT(6)
132 #define LP87565_INT_BUCK01 BIT(5)
133 #define LP87565_NO_SYNC_CLK BIT(4)
134 #define LP87565_TDIE_SD BIT(3)
135 #define LP87565_TDIE_WARN BIT(2)
136 #define LP87565_INT_OVP BIT(1)
137 #define LP87565_I_LOAD_READY BIT(0)
139 #define LP87565_INT_TOP2_RESET_REG BIT(0)
141 #define LP87565_BUCK1_PG_INT BIT(6)
142 #define LP87565_BUCK1_SC_INT BIT(5)
143 #define LP87565_BUCK1_ILIM_INT BIT(4)
144 #define LP87565_BUCK0_PG_INT BIT(2)
145 #define LP87565_BUCK0_SC_INT BIT(1)
146 #define LP87565_BUCK0_ILIM_INT BIT(0)
148 #define LP87565_BUCK3_PG_INT BIT(6)
149 #define LP87565_BUCK3_SC_INT BIT(5)
150 #define LP87565_BUCK3_ILIM_INT BIT(4)
151 #define LP87565_BUCK2_PG_INT BIT(2)
152 #define LP87565_BUCK2_SC_INT BIT(1)
153 #define LP87565_BUCK2_ILIM_INT BIT(0)
155 #define LP87565_SYNC_CLK_STAT BIT(4)
156 #define LP87565_TDIE_SD_STAT BIT(3)
157 #define LP87565_TDIE_WARN_STAT BIT(2)
158 #define LP87565_OVP_STAT BIT(1)
160 #define LP87565_BUCK1_STAT BIT(7)
161 #define LP87565_BUCK1_PG_STAT BIT(6)
162 #define LP87565_BUCK1_ILIM_STAT BIT(4)
163 #define LP87565_BUCK0_STAT BIT(3)
164 #define LP87565_BUCK0_PG_STAT BIT(2)
165 #define LP87565_BUCK0_ILIM_STAT BIT(0)
167 #define LP87565_BUCK3_STAT BIT(7)
168 #define LP87565_BUCK3_PG_STAT BIT(6)
169 #define LP87565_BUCK3_ILIM_STAT BIT(4)
170 #define LP87565_BUCK2_STAT BIT(3)
171 #define LP87565_BUCK2_PG_STAT BIT(2)
172 #define LP87565_BUCK2_ILIM_STAT BIT(0)
174 #define LPL87565_GPIO_MASK BIT(7)
175 #define LPL87565_SYNC_CLK_MASK BIT(4)
176 #define LPL87565_TDIE_WARN_MASK BIT(2)
177 #define LPL87565_I_LOAD_READY_MASK BIT(0)
179 #define LPL87565_RESET_REG_MASK BIT(0)
181 #define LPL87565_BUCK1_PG_MASK BIT(6)
182 #define LPL87565_BUCK1_ILIM_MASK BIT(4)
183 #define LPL87565_BUCK0_PG_MASK BIT(2)
184 #define LPL87565_BUCK0_ILIM_MASK BIT(0)
186 #define LPL87565_BUCK3_PG_MASK BIT(6)
187 #define LPL87565_BUCK3_ILIM_MASK BIT(4)
188 #define LPL87565_BUCK2_PG_MASK BIT(2)
189 #define LPL87565_BUCK2_ILIM_MASK BIT(0)
201 #define LP87565_HALF_DAY BIT(7)
202 #define LP87565_EN_PG0_NINT BIT(6)
203 #define LP87565_PGOOD_SET_DELAY BIT(5)
204 #define LP87565_EN_PGFLT_STAT BIT(4)
205 #define LP87565_PGOOD_WINDOW BIT(2)
206 #define LP87565_PGOOD_OD BIT(1)
207 #define LP87565_PGOOD_POL BIT(0)
209 #define LP87565_PG3_FLT BIT(3)
210 #define LP87565_PG2_FLT BIT(2)
211 #define LP87565_PG1_FLT BIT(1)
212 #define LP87565_PG0_FLT BIT(0)
217 #define LP87565_EN_SPREAD_SPEC BIT(7)
218 #define LP87565_EN_PIN_CTRL_GPIO3 BIT(6)
219 #define LP87565_EN_PIN_SELECT_GPIO3 BIT(5)
220 #define LP87565_EN_PIN_CTRL_GPIO2 BIT(4)
221 #define LP87565_EN_PIN_SELECT_GPIO2 BIT(3)
222 #define LP87565_GPIO3_SEL BIT(2)
223 #define LP87565_GPIO2_SEL BIT(1)
224 #define LP87565_GPIO1_SEL BIT(0)
226 #define LP87565_GOIO3_OD BIT(6)
227 #define LP87565_GOIO2_OD BIT(5)
228 #define LP87565_GOIO1_OD BIT(4)
229 #define LP87565_GOIO3_DIR BIT(2)
230 #define LP87565_GOIO2_DIR BIT(1)
231 #define LP87565_GOIO1_DIR BIT(0)
233 #define LP87565_GOIO3_IN BIT(2)
234 #define LP87565_GOIO2_IN BIT(1)
235 #define LP87565_GOIO1_IN BIT(0)
237 #define LP87565_GOIO3_OUT BIT(2)
238 #define LP87565_GOIO2_OUT BIT(1)
239 #define LP87565_GOIO1_OUT BIT(0)