Lines Matching defs:intel_iommu
428 struct intel_iommu { struct
429 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
430 u64 reg_phys; /* physical address of hw register set */
431 u64 reg_size; /* size of hw register set */
432 u64 cap;
433 u64 ecap;
434 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
435 raw_spinlock_t register_lock; /* protect register handling */
436 int seq_id; /* sequence id of the iommu */
437 int agaw; /* agaw of this iommu */
438 int msagaw; /* max sagaw of this iommu */
439 unsigned int irq, pr_irq;
440 u16 segment; /* PCI segment# */
441 unsigned char name[13]; /* Device Name */
444 unsigned long *domain_ids; /* bitmap of domains */
445 struct dmar_domain ***domains; /* ptr to domains */
446 spinlock_t lock; /* protect context, domain ids */
447 struct root_entry *root_entry; /* virtual address */
449 struct iommu_flush flush;
457 struct pasid_state_entry *pasid_state_table;
458 struct page_req_dsc *prq;
459 unsigned char prq_name[16]; /* Name for PRQ interrupt */
460 u32 pasid_max;
462 struct q_inval *qi; /* Queued invalidation info */
463 u32 *iommu_state; /* Store iommu states between suspend and resume.*/
466 struct ir_table *ir_table; /* Interrupt remapping info */
467 struct irq_domain *ir_domain;
491 struct intel_iommu *iommu; /* IOMMU used by this device */ argument